From 3c8cdf9b60b98c5b408e2cfbcab3160e25e5af5a Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sun, 5 Dec 2010 16:45:02 +0000 Subject: drm/i915: Power Context register is only available for gen4 mobiles The ability to save the hardware context upon powering down the render clock through PWRCTXA is only available on a couple of gen4 chipsets. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a95c69392afc..aba1c33f6407 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5973,7 +5973,7 @@ void intel_init_clock_gating(struct drm_device *dev) "Disable RC6\n"); } - if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { + if (IS_GEN4(dev) && IS_MOBILE(dev)) { if (dev_priv->pwrctx == NULL) dev_priv->pwrctx = intel_alloc_context_page(dev); if (dev_priv->pwrctx) { -- cgit v1.2.3-55-g7522