From cd54fb96e568cf95bad6deb8b070e05643e80935 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 3 Jan 2019 15:23:15 +0100 Subject: drm/tegra: sor: Parse more data from HDA format The HDA format data passed to the SOR from the HDA codec contains more information than just the rate and number of channels. Parse all the fields and store them in an internal structure for subsequent use. While at it, also fix an off-by-one error in the number of channels. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 69 ++++++++++++++++++++++++++++++++++----------- 1 file changed, 53 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/tegra/sor.c') diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index ef8692b7075a..7839223aa040 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -393,6 +393,13 @@ struct tegra_sor_ops { int (*remove)(struct tegra_sor *sor); }; +struct tegra_sor_audio { + unsigned int sample_rate; + unsigned int channels; + unsigned int bits; + bool pcm; +}; + struct tegra_sor { struct host1x_client client; struct tegra_output output; @@ -429,10 +436,7 @@ struct tegra_sor { struct delayed_work scdc; bool scdc_enabled; - struct { - unsigned int sample_rate; - unsigned int channels; - } audio; + struct tegra_sor_audio audio; }; struct tegra_sor_state { @@ -3195,22 +3199,58 @@ static int tegra_sor_parse_dt(struct tegra_sor *sor) return 0; } -static void tegra_hda_parse_format(unsigned int format, unsigned int *rate, - unsigned int *channels) +static void tegra_hda_parse_format(unsigned int format, + struct tegra_sor_audio *audio) { - unsigned int mul, div; + unsigned int mul, div, bits, channels; + + if (format & AC_FMT_TYPE_NON_PCM) + audio->pcm = false; + else + audio->pcm = true; if (format & AC_FMT_BASE_44K) - *rate = 44100; + audio->sample_rate = 44100; else - *rate = 48000; + audio->sample_rate = 48000; mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT; div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT; - *rate = *rate * (mul + 1) / (div + 1); + audio->sample_rate = audio->sample_rate * (mul + 1) / (div + 1); + + switch (format & AC_FMT_BITS_MASK) { + case AC_FMT_BITS_8: + audio->bits = 8; + break; + + case AC_FMT_BITS_16: + audio->bits = 16; + break; + + case AC_FMT_BITS_20: + audio->bits = 20; + break; + + case AC_FMT_BITS_24: + audio->bits = 24; + break; + + case AC_FMT_BITS_32: + audio->bits = 32; + break; + + default: + bits = (format & AC_FMT_BITS_MASK) >> AC_FMT_BITS_SHIFT; + WARN(1, "invalid number of bits: %#x\n", bits); + audio->bits = 8; + break; + } - *channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT; + channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT; + + /* channels are encoded as n - 1 */ + audio->channels = channels + 1; } static irqreturn_t tegra_sor_irq(int irq, void *data) @@ -3225,14 +3265,11 @@ static irqreturn_t tegra_sor_irq(int irq, void *data) value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { - unsigned int format, sample_rate, channels; + unsigned int format; format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; - tegra_hda_parse_format(format, &sample_rate, &channels); - - sor->audio.sample_rate = sample_rate; - sor->audio.channels = channels; + tegra_hda_parse_format(format, &sor->audio); tegra_sor_hdmi_audio_enable(sor); } else { -- cgit v1.2.3-55-g7522 From fad7b80643100d16b157b4367a6d2c7f8b19f812 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 3 Jan 2019 15:23:16 +0100 Subject: drm/tegra: hda: Extract HDA format parsing code This code can be reused for HDMI, so extract it into a reusable function. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/Makefile | 1 + drivers/gpu/drm/tegra/hda.c | 63 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/hda.h | 20 +++++++++++ drivers/gpu/drm/tegra/sor.c | 80 +++++------------------------------------- 4 files changed, 93 insertions(+), 71 deletions(-) create mode 100644 drivers/gpu/drm/tegra/hda.c create mode 100644 drivers/gpu/drm/tegra/hda.h (limited to 'drivers/gpu/drm/tegra/sor.c') diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 2e0d6213f6bc..33c463e8d49f 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -10,6 +10,7 @@ tegra-drm-y := \ dc.o \ output.o \ rgb.o \ + hda.o \ hdmi.o \ mipi-phy.o \ dsi.o \ diff --git a/drivers/gpu/drm/tegra/hda.c b/drivers/gpu/drm/tegra/hda.c new file mode 100644 index 000000000000..94245a18a043 --- /dev/null +++ b/drivers/gpu/drm/tegra/hda.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2019 NVIDIA Corporation + */ + +#include + +#include + +#include "hda.h" + +void tegra_hda_parse_format(unsigned int format, struct tegra_hda_format *fmt) +{ + unsigned int mul, div, bits, channels; + + if (format & AC_FMT_TYPE_NON_PCM) + fmt->pcm = false; + else + fmt->pcm = true; + + if (format & AC_FMT_BASE_44K) + fmt->sample_rate = 44100; + else + fmt->sample_rate = 48000; + + mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT; + div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT; + + fmt->sample_rate *= (mul + 1) / (div + 1); + + switch (format & AC_FMT_BITS_MASK) { + case AC_FMT_BITS_8: + fmt->bits = 8; + break; + + case AC_FMT_BITS_16: + fmt->bits = 16; + break; + + case AC_FMT_BITS_20: + fmt->bits = 20; + break; + + case AC_FMT_BITS_24: + fmt->bits = 24; + break; + + case AC_FMT_BITS_32: + fmt->bits = 32; + break; + + default: + bits = (format & AC_FMT_BITS_MASK) >> AC_FMT_BITS_SHIFT; + WARN(1, "invalid number of bits: %#x\n", bits); + fmt->bits = 8; + break; + } + + channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT; + + /* channels are encoded as n - 1 */ + fmt->channels = channels + 1; +} diff --git a/drivers/gpu/drm/tegra/hda.h b/drivers/gpu/drm/tegra/hda.h new file mode 100644 index 000000000000..77269955a4f2 --- /dev/null +++ b/drivers/gpu/drm/tegra/hda.h @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2019 NVIDIA Corporation + */ + +#ifndef DRM_TEGRA_HDA_H +#define DRM_TEGRA_HDA_H 1 + +#include + +struct tegra_hda_format { + unsigned int sample_rate; + unsigned int channels; + unsigned int bits; + bool pcm; +}; + +void tegra_hda_parse_format(unsigned int format, struct tegra_hda_format *fmt); + +#endif diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 7839223aa040..79602debf231 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -19,8 +19,6 @@ #include -#include - #include #include #include @@ -28,6 +26,7 @@ #include "dc.h" #include "drm.h" +#include "hda.h" #include "sor.h" #include "trace.h" @@ -393,13 +392,6 @@ struct tegra_sor_ops { int (*remove)(struct tegra_sor *sor); }; -struct tegra_sor_audio { - unsigned int sample_rate; - unsigned int channels; - unsigned int bits; - bool pcm; -}; - struct tegra_sor { struct host1x_client client; struct tegra_output output; @@ -436,7 +428,7 @@ struct tegra_sor { struct delayed_work scdc; bool scdc_enabled; - struct tegra_sor_audio audio; + struct tegra_hda_format format; }; struct tegra_sor_state { @@ -2189,7 +2181,7 @@ static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) return err; } - frame.channels = sor->audio.channels; + frame.channels = sor->format.channels; err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); if (err < 0) { @@ -2218,7 +2210,7 @@ static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); /* inject null samples */ - if (sor->audio.channels != 2) + if (sor->format.channels != 2) value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; else value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; @@ -2249,7 +2241,7 @@ static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); - value = (24000 * 4096) / (128 * sor->audio.sample_rate / 1000); + value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); @@ -2262,15 +2254,15 @@ static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); - value = (24000 * 6144) / (128 * sor->audio.sample_rate / 1000); + value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); - value = (24000 * 12288) / (128 * sor->audio.sample_rate / 1000); + value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); - value = (24000 * 24576) / (128 * sor->audio.sample_rate / 1000); + value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); @@ -3199,60 +3191,6 @@ static int tegra_sor_parse_dt(struct tegra_sor *sor) return 0; } -static void tegra_hda_parse_format(unsigned int format, - struct tegra_sor_audio *audio) -{ - unsigned int mul, div, bits, channels; - - if (format & AC_FMT_TYPE_NON_PCM) - audio->pcm = false; - else - audio->pcm = true; - - if (format & AC_FMT_BASE_44K) - audio->sample_rate = 44100; - else - audio->sample_rate = 48000; - - mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT; - div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT; - - audio->sample_rate = audio->sample_rate * (mul + 1) / (div + 1); - - switch (format & AC_FMT_BITS_MASK) { - case AC_FMT_BITS_8: - audio->bits = 8; - break; - - case AC_FMT_BITS_16: - audio->bits = 16; - break; - - case AC_FMT_BITS_20: - audio->bits = 20; - break; - - case AC_FMT_BITS_24: - audio->bits = 24; - break; - - case AC_FMT_BITS_32: - audio->bits = 32; - break; - - default: - bits = (format & AC_FMT_BITS_MASK) >> AC_FMT_BITS_SHIFT; - WARN(1, "invalid number of bits: %#x\n", bits); - audio->bits = 8; - break; - } - - channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT; - - /* channels are encoded as n - 1 */ - audio->channels = channels + 1; -} - static irqreturn_t tegra_sor_irq(int irq, void *data) { struct tegra_sor *sor = data; @@ -3269,7 +3207,7 @@ static irqreturn_t tegra_sor_irq(int irq, void *data) format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; - tegra_hda_parse_format(format, &sor->audio); + tegra_hda_parse_format(format, &sor->format); tegra_sor_hdmi_audio_enable(sor); } else { -- cgit v1.2.3-55-g7522 From 6d6c815daad8ec3469135c310ed39849cbe7752c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Jan 2019 11:00:58 +0100 Subject: drm/tegra: sor: Support device tree crossbar configuration The crossbar configuration is usually the same across all designs for a given SoC generation. But sometimes there are designs that require some other configuration. Implement support for parsing the crossbar configuration from a device tree. If the crossbar configuration is not present in the device tree, fall back to the default crossbar configuration. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/tegra/sor.c') diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 79602debf231..beb8fda25826 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -410,6 +410,8 @@ struct tegra_sor { struct clk *clk_dp; struct clk *clk; + u8 xbar_cfg[5]; + struct drm_dp_aux *aux; struct drm_info_list *debugfs_files; @@ -1814,7 +1816,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) /* XXX not in TRM */ for (value = 0, i = 0; i < 5; i++) - value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | + value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | SOR_XBAR_CTRL_LINK1_XSEL(i, i); tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); @@ -2550,7 +2552,7 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) /* XXX not in TRM */ for (value = 0, i = 0; i < 5; i++) - value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | + value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | SOR_XBAR_CTRL_LINK1_XSEL(i, i); tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); @@ -3171,6 +3173,8 @@ MODULE_DEVICE_TABLE(of, tegra_sor_of_match); static int tegra_sor_parse_dt(struct tegra_sor *sor) { struct device_node *np = sor->dev->of_node; + u32 xbar_cfg[5]; + unsigned int i; u32 value; int err; @@ -3188,6 +3192,17 @@ static int tegra_sor_parse_dt(struct tegra_sor *sor) sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; } + err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); + if (err < 0) { + /* fall back to default per-SoC XBAR configuration */ + for (i = 0; i < 5; i++) + sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; + } else { + /* copy cells to SOR XBAR configuration */ + for (i = 0; i < 5; i++) + sor->xbar_cfg[i] = xbar_cfg[i]; + } + return 0; } -- cgit v1.2.3-55-g7522