From cba1372812fbc740e57c1982970210ab2b804226 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Jan 2018 21:22:44 +0100 Subject: phy: amlogic: phy-meson-gxl-usb2: don't log an error on -EPROBE_DEFER devm_phy_create can return -EPROBE_DEFER if the phy-supply is not ready yet. Silence this warning as the driver framework will re-attempt registering the PHY - this second try works without any errors. So only log actual errors to keep the kernel log free of misleading error messages. Signed-off-by: Martin Blumenstingl Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/amlogic/phy-meson-gxl-usb2.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/phy/amlogic') diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb2.c b/drivers/phy/amlogic/phy-meson-gxl-usb2.c index e90c4ee25dfe..d68c30d3b510 100644 --- a/drivers/phy/amlogic/phy-meson-gxl-usb2.c +++ b/drivers/phy/amlogic/phy-meson-gxl-usb2.c @@ -210,6 +210,7 @@ static int phy_meson_gxl_usb2_probe(struct platform_device *pdev) struct phy_meson_gxl_usb2_priv *priv; struct phy *phy; void __iomem *base; + int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -242,8 +243,11 @@ static int phy_meson_gxl_usb2_probe(struct platform_device *pdev) phy = devm_phy_create(dev, NULL, &phy_meson_gxl_usb2_ops); if (IS_ERR(phy)) { - dev_err(dev, "failed to create PHY\n"); - return PTR_ERR(phy); + ret = PTR_ERR(phy); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to create PHY\n"); + + return ret; } phy_set_drvdata(phy, priv); -- cgit v1.2.3-55-g7522 From bc4a0241d4e1e2381f4c3b53ad0199324549e0a8 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Jan 2018 21:22:42 +0100 Subject: phy: amlogic: phy-meson-gxl-usb2: support the clock and reset line The Meson GXL USB2 PHYs require an additional clock (USB) which has to be enabled. If that clock is disabled then all PHY registers read 0x0. Luckily for us that clock is always enabled (either by harddware defaults, the bootrom, or any of the bootloaders before u-boot/BL3-3). The OTG capable USB2 PHY additionally has a reset line (USB_OTG, which is shared with other components, such as the USB3 PHY for example). Extend the driver so it handles this clock and the shared reset line. We only trigger the reset during the .init phase since it's a shared reset line, so triggering it during the driver's .reset implementation would effectively also only trigger it once anyways. Signed-off-by: Martin Blumenstingl Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/amlogic/phy-meson-gxl-usb2.c | 44 ++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'drivers/phy/amlogic') diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb2.c b/drivers/phy/amlogic/phy-meson-gxl-usb2.c index d68c30d3b510..a92a3fd51e16 100644 --- a/drivers/phy/amlogic/phy-meson-gxl-usb2.c +++ b/drivers/phy/amlogic/phy-meson-gxl-usb2.c @@ -11,11 +11,13 @@ * along with this program. If not, see . */ +#include #include #include #include #include #include +#include #include #include #include @@ -99,6 +101,8 @@ struct phy_meson_gxl_usb2_priv { struct regmap *regmap; enum phy_mode mode; int is_enabled; + struct clk *clk; + struct reset_control *reset; }; static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { @@ -108,6 +112,31 @@ static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { .max_register = U2P_R3, }; +static int phy_meson_gxl_usb2_init(struct phy *phy) +{ + struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = reset_control_reset(priv->reset); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk); + if (ret) + return ret; + + return 0; +} + +static int phy_meson_gxl_usb2_exit(struct phy *phy) +{ + struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); + + clk_disable_unprepare(priv->clk); + + return 0; +} + static int phy_meson_gxl_usb2_reset(struct phy *phy) { struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); @@ -195,6 +224,8 @@ static int phy_meson_gxl_usb2_power_on(struct phy *phy) } static const struct phy_ops phy_meson_gxl_usb2_ops = { + .init = phy_meson_gxl_usb2_init, + .exit = phy_meson_gxl_usb2_exit, .power_on = phy_meson_gxl_usb2_power_on, .power_off = phy_meson_gxl_usb2_power_off, .set_mode = phy_meson_gxl_usb2_set_mode, @@ -241,6 +272,19 @@ static int phy_meson_gxl_usb2_probe(struct platform_device *pdev) if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); + priv->clk = devm_clk_get(dev, "phy"); + if (IS_ERR(priv->clk)) { + ret = PTR_ERR(priv->clk); + if (ret == -ENOENT) + priv->clk = NULL; + else + return ret; + } + + priv->reset = devm_reset_control_get_optional_shared(dev, "phy"); + if (IS_ERR(priv->reset)) + return PTR_ERR(priv->reset); + phy = devm_phy_create(dev, NULL, &phy_meson_gxl_usb2_ops); if (IS_ERR(phy)) { ret = PTR_ERR(phy); -- cgit v1.2.3-55-g7522 From 05818862bc27255e335ee6085d6ce57b6cb01f99 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Jan 2018 21:22:43 +0100 Subject: phy: amlogic: phy-meson-gxl-usb2: default to host mode The USB2 PHY can switch between PHY_MODE_USB_HOST and PHY_MODE_USB_DEVICE. However, it cannot do it on it's own since it requires re-routing of the corresponding USB pins from dwc3 (which is used for host-mode) to dwc2 (which is used for device-mode). Thus we don't need to auto-detect the mode based on the USB controller, which simplifies the driver code. Signed-off-by: Martin Blumenstingl Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/amlogic/Kconfig | 1 - drivers/phy/amlogic/phy-meson-gxl-usb2.c | 15 ++------------- 2 files changed, 2 insertions(+), 14 deletions(-) (limited to 'drivers/phy/amlogic') diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig index cb8f4501652b..ef3625cd25bb 100644 --- a/drivers/phy/amlogic/Kconfig +++ b/drivers/phy/amlogic/Kconfig @@ -18,7 +18,6 @@ config PHY_MESON_GXL_USB2 default ARCH_MESON depends on OF && (ARCH_MESON || COMPILE_TEST) depends on USB_SUPPORT - select USB_COMMON select GENERIC_PHY select REGMAP_MMIO help diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb2.c b/drivers/phy/amlogic/phy-meson-gxl-usb2.c index a92a3fd51e16..f062fc7f0a3a 100644 --- a/drivers/phy/amlogic/phy-meson-gxl-usb2.c +++ b/drivers/phy/amlogic/phy-meson-gxl-usb2.c @@ -20,7 +20,6 @@ #include #include #include -#include /* bits [31:27] are read-only */ #define U2P_R0 0x0 @@ -254,18 +253,8 @@ static int phy_meson_gxl_usb2_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - switch (of_usb_get_dr_mode_by_phy(dev->of_node, -1)) { - case USB_DR_MODE_PERIPHERAL: - priv->mode = PHY_MODE_USB_DEVICE; - break; - case USB_DR_MODE_OTG: - priv->mode = PHY_MODE_USB_OTG; - break; - case USB_DR_MODE_HOST: - default: - priv->mode = PHY_MODE_USB_HOST; - break; - } + /* start in host mode */ + priv->mode = PHY_MODE_USB_HOST; priv->regmap = devm_regmap_init_mmio(dev, base, &phy_meson_gxl_usb2_regmap_conf); -- cgit v1.2.3-55-g7522 From ae91a799fb3cbc6e07718da97b40eb75f782dbaf Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Jan 2018 21:22:45 +0100 Subject: phy: amlogic: phy-meson-gxl-usb2: rename some of the U2P_R2 registers The U2P_R2 register provides "test mode" functionality for bits 17:0. These are only used during SoC development and should be left untouched on production SoC versions. Rename these register definitions to indicate that these are for "test mode" only. While here, also merge the definitions for U2P_R2_DATA_IN_MASK and U2P_R2_DATA_IN_EN_MASK (bits 0:7) because Amlogic's internal documentation suggests that these bits belong together. The old definition was not taken from the documentation but rather from a struct definition in the Amlogic GPL kernel sources. No functional changes. Suggested-by: Yixun Lan Signed-off-by: Martin Blumenstingl Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/amlogic/phy-meson-gxl-usb2.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers/phy/amlogic') diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb2.c b/drivers/phy/amlogic/phy-meson-gxl-usb2.c index f062fc7f0a3a..9f9b5414b97a 100644 --- a/drivers/phy/amlogic/phy-meson-gxl-usb2.c +++ b/drivers/phy/amlogic/phy-meson-gxl-usb2.c @@ -71,12 +71,11 @@ /* bits [31:14] are read-only */ #define U2P_R2 0x8 - #define U2P_R2_DATA_IN_MASK GENMASK(3, 0) - #define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) - #define U2P_R2_ADDR_MASK GENMASK(11, 8) - #define U2P_R2_DATA_OUT_SEL BIT(12) - #define U2P_R2_CLK BIT(13) - #define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) + #define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0) + #define U2P_R2_TESTADDR_MASK GENMASK(11, 8) + #define U2P_R2_TESTDATA_OUT_SEL BIT(12) + #define U2P_R2_TESTCLK BIT(13) + #define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14) #define U2P_R2_ACA_PIN_RANGE_C BIT(18) #define U2P_R2_ACA_PIN_RANGE_B BIT(19) #define U2P_R2_ACA_PIN_RANGE_A BIT(20) -- cgit v1.2.3-55-g7522 From 115de9fd682ccdc6b7c3142287339dbada7a7807 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 3 Mar 2018 19:47:00 +0100 Subject: phy: amlogic: add USB3 PHY support for Meson GXL and GXM This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout). Unfortunately there is no documentation for this PHY in the public S905X datasheet (published for example by Khadas). What we know so far about this PHY: - even though the Meson GXL and GXM SoCs do not expose an USB3 port (the dwc3 controller only has USB2 ports enabled) we need to initialize the USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this initialization high-speed USB devices (especially USB hard disks and thumb drives, slower devices like mice do not seem to be affected) - on some boards the USB3 PHY starts in "device mode" - we want to bring it into a known state (by switching it to host mode for now). - it is responsible for the OTG detection and for switching the first USB2 PHY between host and peripheral (aka device) mode. an interrupt can be used to detect changes between host and device mode. There are five inputs to this register area: - the clock and reset line for the USB3 PHY itself - the clock and reset line for the peripheral mode and OTG detection logic (on the GXL and GXM SoCs these are the same clock and reset line as for the USB3 PHY itself, but Amlogic sees this as two different components - even though they share the same register space - so they have to be passed individually to allow specifying different inputs on other SoCs if needed) - the interrupt for the OTG detection logic The whole OTG detection logic is not implemented yet. Signed-off-by: Martin Blumenstingl Tested-by: Yixun Lan Tested-by: Neil Armstrong Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/amlogic/Kconfig | 12 ++ drivers/phy/amlogic/Makefile | 1 + drivers/phy/amlogic/phy-meson-gxl-usb3.c | 282 +++++++++++++++++++++++++++++++ 3 files changed, 295 insertions(+) create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c (limited to 'drivers/phy/amlogic') diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig index ef3625cd25bb..23fe1cda2f70 100644 --- a/drivers/phy/amlogic/Kconfig +++ b/drivers/phy/amlogic/Kconfig @@ -24,3 +24,15 @@ config PHY_MESON_GXL_USB2 Enable this to support the Meson USB2 PHYs found in Meson GXL and GXM SoCs. If unsure, say N. + +config PHY_MESON_GXL_USB3 + tristate "Meson GXL and GXM USB3 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB3 PHY and OTG detection + IP block found in Meson GXL and GXM SoCs. + If unsure, say N. diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile index cfdc98715c30..4fd8848c194d 100644 --- a/drivers/phy/amlogic/Makefile +++ b/drivers/phy/amlogic/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb3.c b/drivers/phy/amlogic/phy-meson-gxl-usb3.c new file mode 100644 index 000000000000..d37d94ddf9c0 --- /dev/null +++ b/drivers/phy/amlogic/phy-meson-gxl-usb3.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Meson GXL USB3 PHY and OTG mode detection driver + * + * Copyright (C) 2018 Martin Blumenstingl + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USB_R0 0x00 + #define USB_R0_P30_FSEL_MASK GENMASK(5, 0) + #define USB_R0_P30_PHY_RESET BIT(6) + #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7) + #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8) + #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9) + #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14) + #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) + #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) + #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) + #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) + #define USB_R0_U2D_ACT BIT(31) + +#define USB_R1 0x04 + #define USB_R1_U3H_BIGENDIAN_GS BIT(0) + #define USB_R1_U3H_PME_ENABLE BIT(1) + #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2) + #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7) + #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12) + #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) + #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) + #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) + #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) + #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) + +#define USB_R2 0x08 + #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0) + #define USB_R2_P30_CR_READ BIT(16) + #define USB_R2_P30_CR_WRITE BIT(17) + #define USB_R2_P30_CR_CAP_ADDR BIT(18) + #define USB_R2_P30_CR_CAP_DATA BIT(19) + #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) + #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) + +#define USB_R3 0x0c + #define USB_R3_P30_SSC_ENABLE BIT(0) + #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) + #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) + #define USB_R3_P30_REF_SSP_EN BIT(13) + #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16) + #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19) + #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24) + +#define USB_R4 0x10 + #define USB_R4_P21_PORT_RESET_0 BIT(0) + #define USB_R4_P21_SLEEP_M0 BIT(1) + #define USB_R4_MEM_PD_MASK GENMASK(3, 2) + #define USB_R4_P21_ONLY BIT(4) + +#define USB_R5 0x14 + #define USB_R5_ID_DIG_SYNC BIT(0) + #define USB_R5_ID_DIG_REG BIT(1) + #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) + #define USB_R5_ID_DIG_EN_0 BIT(4) + #define USB_R5_ID_DIG_EN_1 BIT(5) + #define USB_R5_ID_DIG_CURR BIT(6) + #define USB_R5_ID_DIG_IRQ BIT(7) + #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) + #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) + +/* read-only register */ +#define USB_R6 0x18 + #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0) + #define USB_R6_P30_CR_ACK BIT(16) + +struct phy_meson_gxl_usb3_priv { + struct regmap *regmap; + enum phy_mode mode; + struct clk *clk_phy; + struct clk *clk_peripheral; + struct reset_control *reset; +}; + +static const struct regmap_config phy_meson_gxl_usb3_regmap_conf = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = USB_R6, +}; + +static int phy_meson_gxl_usb3_power_on(struct phy *phy) +{ + struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); + + regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0, + USB_R5_ID_DIG_EN_0); + regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1, + USB_R5_ID_DIG_EN_1); + regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_TH_MASK, + FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff)); + + return 0; +} + +static int phy_meson_gxl_usb3_power_off(struct phy *phy) +{ + struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); + + regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0, 0); + regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1, 0); + + return 0; +} + +static int phy_meson_gxl_usb3_set_mode(struct phy *phy, enum phy_mode mode) +{ + struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); + + switch (mode) { + case PHY_MODE_USB_HOST: + regmap_update_bits(priv->regmap, USB_R0, USB_R0_U2D_ACT, 0); + regmap_update_bits(priv->regmap, USB_R4, USB_R4_P21_SLEEP_M0, + 0); + break; + + case PHY_MODE_USB_DEVICE: + regmap_update_bits(priv->regmap, USB_R0, USB_R0_U2D_ACT, + USB_R0_U2D_ACT); + regmap_update_bits(priv->regmap, USB_R4, USB_R4_P21_SLEEP_M0, + USB_R4_P21_SLEEP_M0); + break; + + default: + dev_err(&phy->dev, "unsupported PHY mode %d\n", mode); + return -EINVAL; + } + + priv->mode = mode; + + return 0; +} + +static int phy_meson_gxl_usb3_init(struct phy *phy) +{ + struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = reset_control_reset(priv->reset); + if (ret) + goto err; + + ret = clk_prepare_enable(priv->clk_phy); + if (ret) + goto err; + + ret = clk_prepare_enable(priv->clk_peripheral); + if (ret) + goto err_disable_clk_phy; + + ret = phy_meson_gxl_usb3_set_mode(phy, priv->mode); + if (ret) + goto err_disable_clk_peripheral; + + regmap_update_bits(priv->regmap, USB_R1, + USB_R1_U3H_FLADJ_30MHZ_REG_MASK, + FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20)); + + return 0; + +err_disable_clk_peripheral: + clk_disable_unprepare(priv->clk_peripheral); +err_disable_clk_phy: + clk_disable_unprepare(priv->clk_phy); +err: + return ret; +} + +static int phy_meson_gxl_usb3_exit(struct phy *phy) +{ + struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); + + clk_disable_unprepare(priv->clk_peripheral); + clk_disable_unprepare(priv->clk_phy); + + return 0; +} + +static const struct phy_ops phy_meson_gxl_usb3_ops = { + .power_on = phy_meson_gxl_usb3_power_on, + .power_off = phy_meson_gxl_usb3_power_off, + .set_mode = phy_meson_gxl_usb3_set_mode, + .init = phy_meson_gxl_usb3_init, + .exit = phy_meson_gxl_usb3_exit, + .owner = THIS_MODULE, +}; + +static int phy_meson_gxl_usb3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct phy_meson_gxl_usb3_priv *priv; + struct resource *res; + struct phy *phy; + struct phy_provider *phy_provider; + void __iomem *base; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->regmap = devm_regmap_init_mmio(dev, base, + &phy_meson_gxl_usb3_regmap_conf); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->clk_phy = devm_clk_get(dev, "phy"); + if (IS_ERR(priv->clk_phy)) + return PTR_ERR(priv->clk_phy); + + priv->clk_peripheral = devm_clk_get(dev, "peripheral"); + if (IS_ERR(priv->clk_peripheral)) + return PTR_ERR(priv->clk_peripheral); + + priv->reset = devm_reset_control_array_get_shared(dev); + if (IS_ERR(priv->reset)) + return PTR_ERR(priv->reset); + + /* + * default to host mode as hardware defaults and/or boot-loader + * behavior can result in this PHY starting up in device mode. this + * default and the initialization in phy_meson_gxl_usb3_init ensure + * that we reproducibly start in a known mode on all devices. + */ + priv->mode = PHY_MODE_USB_HOST; + + phy = devm_phy_create(dev, np, &phy_meson_gxl_usb3_ops); + if (IS_ERR(phy)) { + ret = PTR_ERR(phy); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to create PHY\n"); + + return ret; + } + + phy_set_drvdata(phy, priv); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id phy_meson_gxl_usb3_of_match[] = { + { .compatible = "amlogic,meson-gxl-usb3-phy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb3_of_match); + +static struct platform_driver phy_meson_gxl_usb3_driver = { + .probe = phy_meson_gxl_usb3_probe, + .driver = { + .name = "phy-meson-gxl-usb3", + .of_match_table = phy_meson_gxl_usb3_of_match, + }, +}; +module_platform_driver(phy_meson_gxl_usb3_driver); + +MODULE_AUTHOR("Martin Blumenstingl "); +MODULE_DESCRIPTION("Meson GXL USB3 PHY and OTG detection driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3-55-g7522