From 5c6366e14d9d4466ae34a1ccbc08dd8738909c1f Mon Sep 17 00:00:00 2001 From: Murthy, Raghuveer Date: Thu, 3 Mar 2011 09:27:58 -0600 Subject: OMAP: DSS2: Adding dss_features for independent core clk divider In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div) field. The lcd_div is common, for deciding the DISPC core functional clock frequency, and the final pixel clock frequency for LCD display. In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR. The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core functional clock configuration. For pixel clock configuration of primary and secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used respectively Signed-off-by: Archit Taneja Signed-off-by: Raghuveer Murthy Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss_features.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/video/omap2/dss/dss_features.h') diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 65d6de7e0feb..569d1b295edd 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -36,6 +36,8 @@ enum dss_feat_id { FEAT_LINEBUFFERSPLIT = 1 << 8, FEAT_ROWREPEATENABLE = 1 << 9, FEAT_RESIZECONF = 1 << 10, + /* Independent core clk divider */ + FEAT_CORE_CLK_DIV = 1 << 11, }; /* DSS register field id */ -- cgit v1.2.3-55-g7522