From fc11fbf9a785b25c5d07f05a30d4169ec39818da Mon Sep 17 00:00:00 2001
From: Saeed Mahameed
Date: Thu, 11 Jun 2015 14:47:28 +0300
Subject: net/mlx5e: Add HW cacheline start padding

Enable HW cacheline start padding and align RX WQE size to cacheline
while considering HW start padding. Also, fix dma_unmap call to use
the correct SKB data buffer size.

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 include/linux/mlx5/device.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'include/linux/mlx5/device.h')

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index b2c43508a737..b943cd9e2097 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -131,6 +131,10 @@ enum {
 	MLX5_INLINE_SEG = 0x80000000,
 };
 
+enum {
+	MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
+};
+
 enum {
 	MLX5_MIN_PKEY_TABLE_SIZE = 128,
 	MLX5_MAX_LOG_PKEY_TABLE  = 5,
-- 
cgit v1.2.3-55-g7522