From f80658137fc8b789a71953adeca194a5a4747427 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 2 Mar 2006 22:41:59 +0000 Subject: [ARM] Move HZ definition into Kconfig Move the HZ definition into Kconfig, and set appropriate defaults for platforms. Remove mostly empty asm/arch/param.h include file. Signed-off-by: Russell King --- include/asm-arm/arch-aaec2000/param.h | 15 --------------- include/asm-arm/arch-at91rm9200/param.h | 28 ---------------------------- include/asm-arm/arch-cl7500/param.h | 5 ----- include/asm-arm/arch-clps711x/param.h | 19 ------------------- include/asm-arm/arch-ebsa110/param.h | 4 ---- include/asm-arm/arch-ebsa285/param.h | 3 --- include/asm-arm/arch-h720x/param.h | 10 ---------- include/asm-arm/arch-imx/param.h | 19 ------------------- include/asm-arm/arch-integrator/param.h | 19 ------------------- include/asm-arm/arch-iop3xx/param.h | 3 --- include/asm-arm/arch-ixp2000/param.h | 3 --- include/asm-arm/arch-ixp4xx/param.h | 3 --- include/asm-arm/arch-l7200/param.h | 19 ------------------- include/asm-arm/arch-lh7a40x/param.h | 9 --------- include/asm-arm/arch-omap/param.h | 8 -------- include/asm-arm/arch-pxa/param.h | 3 --- include/asm-arm/arch-realview/param.h | 19 ------------------- include/asm-arm/arch-rpc/param.h | 3 --- include/asm-arm/arch-s3c2410/param.h | 27 --------------------------- include/asm-arm/arch-sa1100/param.h | 3 --- include/asm-arm/arch-shark/param.h | 5 ----- include/asm-arm/arch-versatile/param.h | 19 ------------------- include/asm-arm/param.h | 7 +------ 23 files changed, 1 insertion(+), 252 deletions(-) delete mode 100644 include/asm-arm/arch-aaec2000/param.h delete mode 100644 include/asm-arm/arch-at91rm9200/param.h delete mode 100644 include/asm-arm/arch-cl7500/param.h delete mode 100644 include/asm-arm/arch-clps711x/param.h delete mode 100644 include/asm-arm/arch-ebsa110/param.h delete mode 100644 include/asm-arm/arch-ebsa285/param.h delete mode 100644 include/asm-arm/arch-h720x/param.h delete mode 100644 include/asm-arm/arch-imx/param.h delete mode 100644 include/asm-arm/arch-integrator/param.h delete mode 100644 include/asm-arm/arch-iop3xx/param.h delete mode 100644 include/asm-arm/arch-ixp2000/param.h delete mode 100644 include/asm-arm/arch-ixp4xx/param.h delete mode 100644 include/asm-arm/arch-l7200/param.h delete mode 100644 include/asm-arm/arch-lh7a40x/param.h delete mode 100644 include/asm-arm/arch-omap/param.h delete mode 100644 include/asm-arm/arch-pxa/param.h delete mode 100644 include/asm-arm/arch-realview/param.h delete mode 100644 include/asm-arm/arch-rpc/param.h delete mode 100644 include/asm-arm/arch-s3c2410/param.h delete mode 100644 include/asm-arm/arch-sa1100/param.h delete mode 100644 include/asm-arm/arch-shark/param.h delete mode 100644 include/asm-arm/arch-versatile/param.h (limited to 'include') diff --git a/include/asm-arm/arch-aaec2000/param.h b/include/asm-arm/arch-aaec2000/param.h deleted file mode 100644 index 139936c2faf2..000000000000 --- a/include/asm-arm/arch-aaec2000/param.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * linux/include/asm-arm/arch-aaec2000/param.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_PARAM_H -#define __ASM_ARCH_PARAM_H - -#endif /* __ASM_ARCH_PARAM_H */ - diff --git a/include/asm-arm/arch-at91rm9200/param.h b/include/asm-arm/arch-at91rm9200/param.h deleted file mode 100644 index 9480f8446852..000000000000 --- a/include/asm-arm/arch-at91rm9200/param.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * include/asm-arm/arch-at91rm9200/param.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_PARAM_H -#define __ASM_ARCH_PARAM_H - -/* - * We use default params - */ - -#endif diff --git a/include/asm-arm/arch-cl7500/param.h b/include/asm-arm/arch-cl7500/param.h deleted file mode 100644 index 974bf69fbb1a..000000000000 --- a/include/asm-arm/arch-cl7500/param.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * linux/include/asm-arm/arch-cl7500/param.h - * - * Copyright (C) 1999 Nexus Electronics Ltd - */ diff --git a/include/asm-arm/arch-clps711x/param.h b/include/asm-arm/arch-clps711x/param.h deleted file mode 100644 index 86f6bd29623d..000000000000 --- a/include/asm-arm/arch-clps711x/param.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/include/asm-arm/arch-clps711x/param.h - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/include/asm-arm/arch-ebsa110/param.h b/include/asm-arm/arch-ebsa110/param.h deleted file mode 100644 index be19b08d1c75..000000000000 --- a/include/asm-arm/arch-ebsa110/param.h +++ /dev/null @@ -1,4 +0,0 @@ -/* - * linux/include/asm-arm/arch-ebsa110/param.h - */ -#define HZ 200 diff --git a/include/asm-arm/arch-ebsa285/param.h b/include/asm-arm/arch-ebsa285/param.h deleted file mode 100644 index 3827103b27a0..000000000000 --- a/include/asm-arm/arch-ebsa285/param.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * linux/include/asm-arm/arch-ebsa285/param.h - */ diff --git a/include/asm-arm/arch-h720x/param.h b/include/asm-arm/arch-h720x/param.h deleted file mode 100644 index 2b80235f9847..000000000000 --- a/include/asm-arm/arch-h720x/param.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * linux/include/asm-arm/arch-h720x/param.h - * - * Copyright (C) 2000 Jungjun Kim - */ - -#ifndef __ASM_ARCH_PARAM_H -#define __ASM_ARCH_PARAM_H - -#endif diff --git a/include/asm-arm/arch-imx/param.h b/include/asm-arm/arch-imx/param.h deleted file mode 100644 index 7c724f03333e..000000000000 --- a/include/asm-arm/arch-imx/param.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/include/asm-arm/arch-imx/param.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/include/asm-arm/arch-integrator/param.h b/include/asm-arm/arch-integrator/param.h deleted file mode 100644 index afa582ff3717..000000000000 --- a/include/asm-arm/arch-integrator/param.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/include/asm-arm/arch-integrator/param.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/include/asm-arm/arch-iop3xx/param.h b/include/asm-arm/arch-iop3xx/param.h deleted file mode 100644 index acf404e87358..000000000000 --- a/include/asm-arm/arch-iop3xx/param.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/param.h - */ diff --git a/include/asm-arm/arch-ixp2000/param.h b/include/asm-arm/arch-ixp2000/param.h deleted file mode 100644 index 2646d9e5919d..000000000000 --- a/include/asm-arm/arch-ixp2000/param.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * linux/include/asm-arm/arch-ixp2000/param.h - */ diff --git a/include/asm-arm/arch-ixp4xx/param.h b/include/asm-arm/arch-ixp4xx/param.h deleted file mode 100644 index 8a757125e5e7..000000000000 --- a/include/asm-arm/arch-ixp4xx/param.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * linux/include/asm-arm/arch-ixp4xx/param.h - */ diff --git a/include/asm-arm/arch-l7200/param.h b/include/asm-arm/arch-l7200/param.h deleted file mode 100644 index 9962a12ab158..000000000000 --- a/include/asm-arm/arch-l7200/param.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/include/asm-arm/arch-l7200/param.h - * - * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) - * Steve Hill (sjhill@cotw.com) - * - * This file contains the hardware definitions for the - * LinkUp Systems L7200 SOC development board. - * - * Changelog: - * 04-21-2000 RS Created L7200 version - * 04-25-2000 SJH Cleaned up file - * 05-03-2000 SJH Change comments and rate - */ - -/* - * See 'time.h' for how the RTC HZ rate is set - */ -#define HZ 128 diff --git a/include/asm-arm/arch-lh7a40x/param.h b/include/asm-arm/arch-lh7a40x/param.h deleted file mode 100644 index acad0bc5deba..000000000000 --- a/include/asm-arm/arch-lh7a40x/param.h +++ /dev/null @@ -1,9 +0,0 @@ -/* include/asm-arm/arch-lh7a40x/param.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h deleted file mode 100644 index face9ad41e97..000000000000 --- a/include/asm-arm/arch-omap/param.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * linux/include/asm-arm/arch-omap/param.h - * - */ - -#ifdef CONFIG_OMAP_32K_TIMER_HZ -#define HZ CONFIG_OMAP_32K_TIMER_HZ -#endif diff --git a/include/asm-arm/arch-pxa/param.h b/include/asm-arm/arch-pxa/param.h deleted file mode 100644 index 3197d82d7573..000000000000 --- a/include/asm-arm/arch-pxa/param.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/param.h - */ diff --git a/include/asm-arm/arch-realview/param.h b/include/asm-arm/arch-realview/param.h deleted file mode 100644 index 89b1235d32bd..000000000000 --- a/include/asm-arm/arch-realview/param.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/include/asm-arm/arch-realview/param.h - * - * Copyright (C) 2002 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/include/asm-arm/arch-rpc/param.h b/include/asm-arm/arch-rpc/param.h deleted file mode 100644 index 721dcd658858..000000000000 --- a/include/asm-arm/arch-rpc/param.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * linux/include/asm-arm/arch-rpc/param.h - */ diff --git a/include/asm-arm/arch-s3c2410/param.h b/include/asm-arm/arch-s3c2410/param.h deleted file mode 100644 index 483d3f149883..000000000000 --- a/include/asm-arm/arch-s3c2410/param.h +++ /dev/null @@ -1,27 +0,0 @@ -/* linux/include/asm-arm/arch-s3c2410/param.h - * - * (c) 2003 Simtec Electronics - * Ben Dooks - * - * S3C2410 - Machine parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 02-Sep-2003 BJD Created file - * 12-Mar-2004 BJD Added include protection -*/ - -#ifndef __ASM_ARCH_PARAM_H -#define __ASM_ARCH_PARAM_H - -/* we cannot get our timer down to 100Hz with the setup as is, but we can - * manage 200 clock ticks per second... if this is a problem, we can always - * add a software pre-scaler to the evil timer systems. -*/ - -#define HZ 200 - -#endif /* __ASM_ARCH_PARAM_H */ diff --git a/include/asm-arm/arch-sa1100/param.h b/include/asm-arm/arch-sa1100/param.h deleted file mode 100644 index 867488909ecd..000000000000 --- a/include/asm-arm/arch-sa1100/param.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/param.h - */ diff --git a/include/asm-arm/arch-shark/param.h b/include/asm-arm/arch-shark/param.h deleted file mode 100644 index 997eeb71de00..000000000000 --- a/include/asm-arm/arch-shark/param.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * linux/include/asm-arm/arch-shark/param.h - * - * by Alexander Schulz - */ diff --git a/include/asm-arm/arch-versatile/param.h b/include/asm-arm/arch-versatile/param.h deleted file mode 100644 index 34b897335f87..000000000000 --- a/include/asm-arm/arch-versatile/param.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/include/asm-arm/arch-versatile/param.h - * - * Copyright (C) 2002 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/include/asm-arm/param.h b/include/asm-arm/param.h index 94223d4d7e88..15806468ba72 100644 --- a/include/asm-arm/param.h +++ b/include/asm-arm/param.h @@ -11,12 +11,7 @@ #define __ASM_PARAM_H #ifdef __KERNEL__ -# include /* for kernel version of HZ */ - -# ifndef HZ -# define HZ 100 /* Internal kernel timer frequency */ -# endif - +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ # define USER_HZ 100 /* User interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #else -- cgit v1.2.3-55-g7522 From 411ef7f4cf1684ca7977c7917fd841ea091c5b26 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Mar 2006 10:37:07 +0000 Subject: [ARM] Remove asm/arch/irq.h asm/arch/irq.h used to be included from asm/irq.h, but was removed from the ARM kernel a long time ago. Consequently, the contents of asm/arch/irq.h (which mostly contain a definition for fixup_irq()) have not been used. Hence, remove asm/arch/irq.h. Some machine support files incorrectly included this file, making little or no use of the contents. Move the contents to a local include file, and remove those include statements as well. Signed-off-by: Russell King --- arch/arm/mach-lh7a40x/common.h | 1 + arch/arm/mach-lh7a40x/irq-kev7a400.c | 1 + arch/arm/mach-lh7a40x/irq-lh7a400.c | 2 +- arch/arm/mach-lh7a40x/irq-lh7a404.c | 3 ++- arch/arm/mach-lh7a40x/irq-lpd7a40x.c | 1 + arch/arm/mach-pxa/corgi.c | 1 - arch/arm/mach-pxa/poodle.c | 1 - arch/arm/mach-pxa/spitz.c | 1 - arch/arm/mach-pxa/tosa.c | 1 - include/asm-arm/arch-h720x/irq.h | 14 -------------- include/asm-arm/arch-imx/irq.h | 20 -------------------- include/asm-arm/arch-ixp2000/irq.h | 13 ------------- include/asm-arm/arch-ixp4xx/irq.h | 13 ------------- include/asm-arm/arch-lh7a40x/irq.h | 11 ----------- include/asm-arm/arch-pxa/irq.h | 14 -------------- 15 files changed, 6 insertions(+), 91 deletions(-) delete mode 100644 include/asm-arm/arch-h720x/irq.h delete mode 100644 include/asm-arm/arch-imx/irq.h delete mode 100644 include/asm-arm/arch-ixp2000/irq.h delete mode 100644 include/asm-arm/arch-ixp4xx/irq.h delete mode 100644 include/asm-arm/arch-lh7a40x/irq.h delete mode 100644 include/asm-arm/arch-pxa/irq.h (limited to 'include') diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h index 578a52461fdb..ea8de7e3ab1b 100644 --- a/arch/arm/mach-lh7a40x/common.h +++ b/arch/arm/mach-lh7a40x/common.h @@ -12,5 +12,6 @@ extern struct sys_timer lh7a40x_timer; extern void lh7a400_init_irq (void); extern void lh7a404_init_irq (void); +extern void lh7a40x_init_board_irq (void); #define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs) diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c index 691bb09232a5..8535764d89ca 100644 --- a/arch/arm/mach-lh7a40x/irq-kev7a400.c +++ b/arch/arm/mach-lh7a40x/irq-kev7a400.c @@ -16,6 +16,7 @@ #include #include +#include "common.h" /* KEV7a400 CPLD IRQ handling */ diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c index f334d81c2cd8..f9fdefef6d6f 100644 --- a/arch/arm/mach-lh7a40x/irq-lh7a400.c +++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c @@ -16,9 +16,9 @@ #include #include #include -#include #include +#include "common.h" /* CPU IRQ handling */ diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c index 122fadabc97d..e902e3d87da4 100644 --- a/arch/arm/mach-lh7a40x/irq-lh7a404.c +++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c @@ -16,9 +16,10 @@ #include #include #include -#include #include +#include "common.h" + #define USE_PRIORITIES /* See Documentation/arm/Sharp-LH/VectoredInterruptController for more diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c index 6262d449120c..dcb4e17b9419 100644 --- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c +++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c @@ -19,6 +19,7 @@ #include #include +#include "common.h" static void lh7a40x_ack_cpld_irq (u32 irq) { diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 7ffd2de8f2f3..68923b1d2b62 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -32,7 +32,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 911e6ff5a9bd..b45560a8f6c4 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index c094d99ebf56..30ec317bbb97 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -33,7 +33,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index d168286ed470..66ec71756d0f 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -34,7 +34,6 @@ #include #include -#include #include #include diff --git a/include/asm-arm/arch-h720x/irq.h b/include/asm-arm/arch-h720x/irq.h deleted file mode 100644 index b3821e957aa4..000000000000 --- a/include/asm-arm/arch-h720x/irq.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * include/asm-arm/arch-h720x/irq.h - * - * Copyright (C) 2000-2002 Jungjun Kim - * (C) 2003 Robert Schwebel - * (C) 2003 Thomas Gleixner - */ - -#ifndef __ASM_ARCH_IRQ_H -#define __ASM_ARCH_IRQ_H - -extern void __init h720x_init_irq (void); - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/include/asm-arm/arch-imx/irq.h b/include/asm-arm/arch-imx/irq.h deleted file mode 100644 index 545e065d2325..000000000000 --- a/include/asm-arm/arch-imx/irq.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * linux/include/asm-arm/arch-imxads/irq.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define fixup_irq(i) (i) diff --git a/include/asm-arm/arch-ixp2000/irq.h b/include/asm-arm/arch-ixp2000/irq.h deleted file mode 100644 index ba00b23f9828..000000000000 --- a/include/asm-arm/arch-ixp2000/irq.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * linux/include/asm-arm/arch-ixp2000/irq.h - * - * Copyright (C) 2002 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define fixup_irq(irq) (irq) - - diff --git a/include/asm-arm/arch-ixp4xx/irq.h b/include/asm-arm/arch-ixp4xx/irq.h deleted file mode 100644 index 87da70695f0a..000000000000 --- a/include/asm-arm/arch-ixp4xx/irq.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * irq.h - * - * Copyright (C) 2002 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#define fixup_irq(irq) (irq) - diff --git a/include/asm-arm/arch-lh7a40x/irq.h b/include/asm-arm/arch-lh7a40x/irq.h deleted file mode 100644 index 0f5f0b10f6ca..000000000000 --- a/include/asm-arm/arch-lh7a40x/irq.h +++ /dev/null @@ -1,11 +0,0 @@ -/* include/asm-arm/arch-lh7a40x/irq.h - * - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -void __init lh7a40x_init_board_irq (void); diff --git a/include/asm-arm/arch-pxa/irq.h b/include/asm-arm/arch-pxa/irq.h deleted file mode 100644 index 48c60f5eff6a..000000000000 --- a/include/asm-arm/arch-pxa/irq.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/irq.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define fixup_irq(x) (x) - -- cgit v1.2.3-55-g7522 From 548153663bbf33ca7c244a6bbddd82c26a17c331 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Mar 2006 15:43:04 +0000 Subject: [ARM] Rename chipdata to 'base' and make it an iomem pointer In all current use cases, "chipdata" is used to store an iomem address. Mark it with __iomem, and rename it to 'base'. Leave the accessor macros alone. Signed-off-by: Russell King --- arch/arm/common/locomo.c | 42 ++++++++++++++++++++--------------------- arch/arm/mach-at91rm9200/gpio.c | 4 ++-- include/asm-arm/mach/irq.h | 6 +++--- 3 files changed, 26 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 23609400a8e2..787e0d027f04 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -60,7 +60,7 @@ struct locomo { unsigned long phys; unsigned int irq; spinlock_t lock; - void *base; + void __iomem *base; }; struct locomo_dev_info { @@ -162,7 +162,7 @@ static void locomo_handler(unsigned int irq, struct irqdesc *desc, { int req, i; struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); /* Acknowledge the parent IRQ */ desc->chip->ack(irq); @@ -189,7 +189,7 @@ static void locomo_ack_irq(unsigned int irq) static void locomo_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_ICR); r &= ~(0x0010 << (irq - LOCOMO_IRQ_START)); @@ -198,7 +198,7 @@ static void locomo_mask_irq(unsigned int irq) static void locomo_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_ICR); r |= (0x0010 << (irq - LOCOMO_IRQ_START)); @@ -215,7 +215,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) { struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) { d = irq_desc + LOCOMO_IRQ_KEY_START; @@ -225,7 +225,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc, static void locomo_key_ack_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START)); @@ -234,7 +234,7 @@ static void locomo_key_ack_irq(unsigned int irq) static void locomo_key_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START)); @@ -243,7 +243,7 @@ static void locomo_key_mask_irq(unsigned int irq) static void locomo_key_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START)); @@ -261,7 +261,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc, { int req, i; struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); req = locomo_readl(mapbase + LOCOMO_GIR) & locomo_readl(mapbase + LOCOMO_GPD) & @@ -280,7 +280,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc, static void locomo_gpio_ack_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_GWE); r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); @@ -297,7 +297,7 @@ static void locomo_gpio_ack_irq(unsigned int irq) static void locomo_gpio_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_GIE); r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); @@ -306,7 +306,7 @@ static void locomo_gpio_mask_irq(unsigned int irq) static void locomo_gpio_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_GIE); r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); @@ -323,7 +323,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) { struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) { d = irq_desc + LOCOMO_IRQ_LT_START; @@ -333,7 +333,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc, static void locomo_lt_ack_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_LTINT); r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START)); @@ -342,7 +342,7 @@ static void locomo_lt_ack_irq(unsigned int irq) static void locomo_lt_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_LTINT); r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START)); @@ -351,7 +351,7 @@ static void locomo_lt_mask_irq(unsigned int irq) static void locomo_lt_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_LTINT); r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START)); @@ -369,7 +369,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc, { int req, i; struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); req = locomo_readl(mapbase + LOCOMO_SPIIR) & 0x000F; if (req) { @@ -386,7 +386,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc, static void locomo_spi_ack_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_SPIWE); r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); @@ -403,7 +403,7 @@ static void locomo_spi_ack_irq(unsigned int irq) static void locomo_spi_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_SPIIE); r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); @@ -412,7 +412,7 @@ static void locomo_spi_mask_irq(unsigned int irq) static void locomo_spi_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_SPIIE); r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); @@ -428,7 +428,7 @@ static struct irqchip locomo_spi_chip = { static void locomo_setup_irq(struct locomo *lchip) { int irq; - void *irqbase = lchip->base; + void __iomem *irqbase = lchip->base; /* * Install handler for IRQ_LOCOMO_HW. diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c index 0e396feec468..5ab46274e1a3 100644 --- a/arch/arm/mach-at91rm9200/gpio.c +++ b/arch/arm/mach-at91rm9200/gpio.c @@ -261,7 +261,7 @@ static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs void __iomem *pio; u32 isr; - pio = (void __force __iomem *) desc->chipdata; + pio = desc->base; /* temporarily mask (level sensitive) parent IRQ */ desc->chip->ack(irq); @@ -312,7 +312,7 @@ void __init at91_gpio_irq_setup(unsigned banks) __raw_writel(~0, controller + PIO_IDR); set_irq_data(id, (void *) pin); - set_irq_chipdata(id, (void __force *) controller); + set_irq_chipdata(id, controller); for (i = 0; i < 32; i++, pin++) { set_irq_chip(pin, &gpio_irqchip); diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h index 0ce6ca588d8c..76d05244c632 100644 --- a/include/asm-arm/mach/irq.h +++ b/include/asm-arm/mach/irq.h @@ -61,7 +61,7 @@ struct irqdesc { struct irqchip *chip; struct irqaction *action; struct list_head pend; - void *chipdata; + void __iomem *base; void *data; unsigned int disable_depth; @@ -113,8 +113,8 @@ void __set_irq_handler(unsigned int irq, irq_handler_t, int); #define set_irq_handler(irq,handler) __set_irq_handler(irq,handler,0) #define set_irq_chained_handler(irq,handler) __set_irq_handler(irq,handler,1) #define set_irq_data(irq,d) do { irq_desc[irq].data = d; } while (0) -#define set_irq_chipdata(irq,d) do { irq_desc[irq].chipdata = d; } while (0) -#define get_irq_chipdata(irq) (irq_desc[irq].chipdata) +#define set_irq_chipdata(irq,d) do { irq_desc[irq].base = d; } while (0) +#define get_irq_chipdata(irq) (irq_desc[irq].base) void set_irq_chip(unsigned int irq, struct irqchip *); void set_irq_flags(unsigned int irq, unsigned int flags); -- cgit v1.2.3-55-g7522 From 824b5b5e59472c89bc508afa5c453547c91ed53b Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Mar 2006 15:44:29 +0000 Subject: [ARM] Adapt vic.c to allow for multiple VICs in a system. Some SoCs have multiple VIC devices. Adapt the generic vic code to allow multiple implementations to be handled. Signed-off-by: Russell King --- arch/arm/common/vic.c | 49 +++++++++++++++++++++++------------------- arch/arm/mach-versatile/core.c | 2 +- include/asm-arm/hardware/vic.h | 2 +- 3 files changed, 29 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index a45ed1687a59..a19bc4a6196d 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -22,22 +22,21 @@ #include #include -#include #include #include -static void __iomem *vic_base; - static void vic_mask_irq(unsigned int irq) { - irq -= IRQ_VIC_START; - writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR); + void __iomem *base = get_irq_chipdata(irq); + irq &= 31; + writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); } static void vic_unmask_irq(unsigned int irq) { - irq -= IRQ_VIC_START; - writel(1 << irq, vic_base + VIC_INT_ENABLE); + void __iomem *base = get_irq_chipdata(irq); + irq &= 31; + writel(1 << irq, base + VIC_INT_ENABLE); } static struct irqchip vic_chip = { @@ -46,43 +45,49 @@ static struct irqchip vic_chip = { .unmask = vic_unmask_irq, }; -void __init vic_init(void __iomem *base, u32 vic_sources) +/** + * vic_init - initialise a vectored interrupt controller + * @base: iomem base address + * @irq_start: starting interrupt number, must be muliple of 32 + * @vic_sources: bitmask of interrupt sources to allow + */ +void __init vic_init(void __iomem *base, unsigned int irq_start, + u32 vic_sources) { unsigned int i; - vic_base = base; - /* Disable all interrupts initially. */ - writel(0, vic_base + VIC_INT_SELECT); - writel(0, vic_base + VIC_INT_ENABLE); - writel(~0, vic_base + VIC_INT_ENABLE_CLEAR); - writel(0, vic_base + VIC_IRQ_STATUS); - writel(0, vic_base + VIC_ITCR); - writel(~0, vic_base + VIC_INT_SOFT_CLEAR); + writel(0, base + VIC_INT_SELECT); + writel(0, base + VIC_INT_ENABLE); + writel(~0, base + VIC_INT_ENABLE_CLEAR); + writel(0, base + VIC_IRQ_STATUS); + writel(0, base + VIC_ITCR); + writel(~0, base + VIC_INT_SOFT_CLEAR); /* * Make sure we clear all existing interrupts */ - writel(0, vic_base + VIC_VECT_ADDR); + writel(0, base + VIC_VECT_ADDR); for (i = 0; i < 19; i++) { unsigned int value; - value = readl(vic_base + VIC_VECT_ADDR); - writel(value, vic_base + VIC_VECT_ADDR); + value = readl(base + VIC_VECT_ADDR); + writel(value, base + VIC_VECT_ADDR); } for (i = 0; i < 16; i++) { - void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4); + void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); writel(VIC_VECT_CNTL_ENABLE | i, reg); } - writel(32, vic_base + VIC_DEF_VECT_ADDR); + writel(32, base + VIC_DEF_VECT_ADDR); for (i = 0; i < 32; i++) { - unsigned int irq = IRQ_VIC_START + i; + unsigned int irq = irq_start + i; set_irq_chip(irq, &vic_chip); + set_irq_chipdata(irq, base); if (vic_sources & (1 << i)) { set_irq_handler(irq, do_level_IRQ); diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 9ebbe808b41d..799697d32dec 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -112,7 +112,7 @@ void __init versatile_init_irq(void) { unsigned int i; - vic_init(VA_VIC_BASE, ~(1 << 31)); + vic_init(VA_VIC_BASE, IRQ_VIC_START, ~(1 << 31)); set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq); enable_irq(IRQ_VICSOURCE31); diff --git a/include/asm-arm/hardware/vic.h b/include/asm-arm/hardware/vic.h index 81825eb54c9e..ed9ca3736a0b 100644 --- a/include/asm-arm/hardware/vic.h +++ b/include/asm-arm/hardware/vic.h @@ -39,7 +39,7 @@ #define VIC_VECT_CNTL_ENABLE (1 << 5) #ifndef __ASSEMBLY__ -void vic_init(void __iomem *base, u32 vic_sources); +void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); #endif #endif -- cgit v1.2.3-55-g7522 From 22398f57b6372f3150f9ebb4b6d0aa4bf98c5dfb Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Mar 2006 15:55:01 +0000 Subject: [ARM] Fix SA1100 debug-macros.S This needs asm/hardware.h - include it. Signed-off-by: Russell King --- include/asm-arm/arch-sa1100/debug-macro.S | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-arm/arch-sa1100/debug-macro.S b/include/asm-arm/arch-sa1100/debug-macro.S index 755fa3453862..267c317a7408 100644 --- a/include/asm-arm/arch-sa1100/debug-macro.S +++ b/include/asm-arm/arch-sa1100/debug-macro.S @@ -10,6 +10,7 @@ * published by the Free Software Foundation. * */ +#include .macro addruart,rx mrc p15, 0, \rx, c1, c0 -- cgit v1.2.3-55-g7522 From 268099e3ccca5a988632ce18abd21d809d632ddc Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 16 Mar 2006 20:40:25 +0000 Subject: [ARM] Collect 8250-based debug implementations together Several ARM machine implementations used an 8250 compatible port for debugging purposes, and indepdently implemented the low level debug macros every time. Provide a common implementation and convert these implementations to use this version. Signed-off-by: Russell King --- include/asm-arm/arch-cl7500/debug-macro.S | 14 ++------------ include/asm-arm/arch-ebsa110/debug-macro.S | 19 +++---------------- include/asm-arm/arch-ebsa285/debug-macro.S | 18 +++--------------- include/asm-arm/arch-iop3xx/debug-macro.S | 19 +++---------------- include/asm-arm/arch-ixp4xx/debug-macro.S | 15 ++------------- include/asm-arm/arch-pxa/debug-macro.S | 17 ++--------------- include/asm-arm/arch-rpc/debug-macro.S | 19 +++---------------- include/asm-arm/hardware/debug-8250.S | 29 +++++++++++++++++++++++++++++ 8 files changed, 47 insertions(+), 103 deletions(-) create mode 100644 include/asm-arm/hardware/debug-8250.S (limited to 'include') diff --git a/include/asm-arm/arch-cl7500/debug-macro.S b/include/asm-arm/arch-cl7500/debug-macro.S index a5d489d7955a..9a2b67d24098 100644 --- a/include/asm-arm/arch-cl7500/debug-macro.S +++ b/include/asm-arm/arch-cl7500/debug-macro.S @@ -17,15 +17,5 @@ orr \rx, \rx, #0x00000be0 .endm - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro busyuart,rd,rx - .endm - - .macro waituart,rd,rx -1001: ldrb \rd, [\rx, #0x14] - tst \rd, #0x20 - beq 1001b - .endm +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-ebsa110/debug-macro.S b/include/asm-arm/arch-ebsa110/debug-macro.S index dcd03a40c502..f61cadabe0ec 100644 --- a/include/asm-arm/arch-ebsa110/debug-macro.S +++ b/include/asm-arm/arch-ebsa110/debug-macro.S @@ -16,19 +16,6 @@ orr \rx, \rx, #0x00000be0 .endm - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro busyuart,rd,rx -1002: ldrb \rd, [\rx, #0x14] - and \rd, \rd, #0x60 - teq \rd, #0x60 - bne 1002b - .endm - - .macro waituart,rd,rx -1001: ldrb \rd, [\rx, #0x18] - tst \rd, #0x10 - beq 1001b - .endm +#define UART_SHIFT 2 +#define FLOW_CONTROL +#include diff --git a/include/asm-arm/arch-ebsa285/debug-macro.S b/include/asm-arm/arch-ebsa285/debug-macro.S index 97d15fc629af..b48cec4a0c45 100644 --- a/include/asm-arm/arch-ebsa285/debug-macro.S +++ b/include/asm-arm/arch-ebsa285/debug-macro.S @@ -23,22 +23,10 @@ orr \rx, \rx, #0x000003f8 .endm - .macro senduart,rd,rx - strb \rd, [\rx] - .endm +#define UART_SHIFT 0 +#define FLOW_CONTROL +#include - .macro busyuart,rd,rx -1002: ldrb \rd, [\rx, #0x5] - and \rd, \rd, #0x60 - teq \rd, #0x60 - bne 1002b - .endm - - .macro waituart,rd,rx -1001: ldrb \rd, [\rx, #0x6] - tst \rd, #0x10 - beq 1001b - .endm #else /* For EBSA285 debugging */ .equ dc21285_high, ARMCSR_BASE & 0xff000000 diff --git a/include/asm-arm/arch-iop3xx/debug-macro.S b/include/asm-arm/arch-iop3xx/debug-macro.S index cc15f80ebd9a..ce007e531994 100644 --- a/include/asm-arm/arch-iop3xx/debug-macro.S +++ b/include/asm-arm/arch-iop3xx/debug-macro.S @@ -28,21 +28,8 @@ #endif .endm - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro busyuart,rd,rx -1002: ldrb \rd, [\rx, #0x5] - and \rd, \rd, #0x60 - teq \rd, #0x60 - bne 1002b - .endm - - .macro waituart,rd,rx #if !defined(CONFIG_ARCH_IQ80321) || !defined(CONFIG_ARCH_IQ31244) || !defined(CONFIG_ARCH_IQ80331) -1001: ldrb \rd, [\rx, #0x6] - tst \rd, #0x10 - beq 1001b +#define FLOW_CONTROL #endif - .endm +#define UART_SHIFT 0 +#include diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S index 2e23651e217f..37bc8ef23e67 100644 --- a/include/asm-arm/arch-ixp4xx/debug-macro.S +++ b/include/asm-arm/arch-ixp4xx/debug-macro.S @@ -20,16 +20,5 @@ @ byte writes used - Big Endian. .endm - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro waituart,rd,rx -1002: ldrb \rd, [\rx, #0x14] - and \rd, \rd, #0x60 @ check THRE and TEMT bits - teq \rd, #0x60 - bne 1002b - .endm - - .macro busyuart,rd,rx - .endm +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S index b6ec68879176..9012cbc0ad8b 100644 --- a/include/asm-arm/arch-pxa/debug-macro.S +++ b/include/asm-arm/arch-pxa/debug-macro.S @@ -21,18 +21,5 @@ orr \rx, \rx, #0x00100000 .endm - .macro senduart,rd,rx - str \rd, [\rx, #0] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #0x14] - tst \rd, #(1 << 6) - beq 1002b - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x14] - tst \rd, #(1 << 5) - beq 1001b - .endm +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-rpc/debug-macro.S b/include/asm-arm/arch-rpc/debug-macro.S index 456d3d754c3d..c634c8d8f4a1 100644 --- a/include/asm-arm/arch-rpc/debug-macro.S +++ b/include/asm-arm/arch-rpc/debug-macro.S @@ -20,19 +20,6 @@ orr \rx, \rx, #0x00000fe0 .endm - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro busyuart,rd,rx -1001: ldrb \rd, [\rx, #0x14] - and \rd, \rd, #0x60 - teq \rd, #0x60 - bne 1001b - .endm - - .macro waituart,rd,rx -1001: ldrb \rd, [\rx, #0x18] - tst \rd, #0x10 - beq 1001b - .endm +#define UART_SHIFT 2 +#define FLOW_CONTROL +#include diff --git a/include/asm-arm/hardware/debug-8250.S b/include/asm-arm/hardware/debug-8250.S new file mode 100644 index 000000000000..4594fea91ec1 --- /dev/null +++ b/include/asm-arm/hardware/debug-8250.S @@ -0,0 +1,29 @@ +/* + * linux/include/asm-arm/hardware/debug-8250.h + * + * Copyright (C) 1994-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include + + .macro senduart,rd,rx + strb \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + .macro waituart,rd,rx +#ifdef FLOW_CONTROL +1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] + tst \rd, #UART_MSR_CTS + beq 1001b +#endif + .endm -- cgit v1.2.3-55-g7522 From 71dccd0f158a8077c92d51f213b55991b7a0e47e Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 16 Mar 2006 20:50:34 +0000 Subject: [ARM] Collect Primecell PL01x-based debug implementations together Several ARM machine implementations used a PL01x primecell compatible serial port for debugging purposes, and indepdently implemented the low level debug macros every time. Provide a common implementation and convert these implementations to use this version. Signed-off-by: Russell King --- include/asm-arm/arch-integrator/debug-macro.S | 18 +---------------- include/asm-arm/arch-realview/debug-macro.S | 18 +---------------- include/asm-arm/arch-versatile/debug-macro.S | 18 +---------------- include/asm-arm/hardware/debug-pl01x.S | 29 +++++++++++++++++++++++++++ 4 files changed, 32 insertions(+), 51 deletions(-) create mode 100644 include/asm-arm/hardware/debug-pl01x.S (limited to 'include') diff --git a/include/asm-arm/arch-integrator/debug-macro.S b/include/asm-arm/arch-integrator/debug-macro.S index 031d30941791..85b327c352df 100644 --- a/include/asm-arm/arch-integrator/debug-macro.S +++ b/include/asm-arm/arch-integrator/debug-macro.S @@ -11,8 +11,6 @@ * */ -#include - .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? @@ -21,18 +19,4 @@ addne \rx, \rx, #0x16000000 >> 4 .endm - .macro senduart,rd,rx - strb \rd, [\rx, #UART01x_DR] - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full - bne 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy - bne 1001b - .endm +#include diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S index 017ad996848d..f17efc65518a 100644 --- a/include/asm-arm/arch-realview/debug-macro.S +++ b/include/asm-arm/arch-realview/debug-macro.S @@ -11,8 +11,6 @@ * */ -#include - .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? @@ -21,18 +19,4 @@ orr \rx, \rx, #0x00009000 .endm - .macro senduart,rd,rx - strb \rd, [\rx, #UART01x_DR] - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full - bne 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy - bne 1001b - .endm +#include diff --git a/include/asm-arm/arch-versatile/debug-macro.S b/include/asm-arm/arch-versatile/debug-macro.S index ef6167116dbb..fe106d184e62 100644 --- a/include/asm-arm/arch-versatile/debug-macro.S +++ b/include/asm-arm/arch-versatile/debug-macro.S @@ -11,8 +11,6 @@ * */ -#include - .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? @@ -22,18 +20,4 @@ orr \rx, \rx, #0x00001000 .endm - .macro senduart,rd,rx - strb \rd, [\rx, #UART01x_DR] - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full - bne 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy - bne 1001b - .endm +#include diff --git a/include/asm-arm/hardware/debug-pl01x.S b/include/asm-arm/hardware/debug-pl01x.S new file mode 100644 index 000000000000..db0d0f7de5e9 --- /dev/null +++ b/include/asm-arm/hardware/debug-pl01x.S @@ -0,0 +1,29 @@ +/* linux/include/asm-arm/arch-integrator/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ +#include + + .macro senduart,rd,rx + strb \rd, [\rx, #UART01x_DR] + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #UART01x_FR] + tst \rd, #UART01x_FR_TXFF + bne 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #UART01x_FR] + tst \rd, #UART01x_FR_BUSY + bne 1001b + .endm -- cgit v1.2.3-55-g7522 From a61ea9326d9ba94bcdc21f36bb74aa203657c58f Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Mon, 20 Mar 2006 17:10:01 +0000 Subject: [ARM] 3261/2: remove phys_ram from struct machine_desc (part 3) Patch from Nicolas Pitre This field is redundent since it must be equal to PHYS_OFFSET anyway. There is no reference to it anymore so remove it at last. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/kernel/head.S | 7 +++---- include/asm-arm/mach/arch.h | 5 +---- 2 files changed, 4 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 1aca1775b28f..84277fe818a1 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -28,10 +28,9 @@ #define PROCINFO_INITFUNC 12 #define MACHINFO_TYPE 0 -#define MACHINFO_PHYSRAM 4 -#define MACHINFO_PHYSIO 8 -#define MACHINFO_PGOFFIO 12 -#define MACHINFO_NAME 16 +#define MACHINFO_PHYSIO 4 +#define MACHINFO_PGOFFIO 8 +#define MACHINFO_NAME 12 #define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET) diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h index 2cd57b4d64d9..fd2f9bf4dcc6 100644 --- a/include/asm-arm/mach/arch.h +++ b/include/asm-arm/mach/arch.h @@ -10,19 +10,16 @@ #ifndef __ASSEMBLY__ -#include - struct tag; struct meminfo; struct sys_timer; struct machine_desc { /* - * Note! The first five elements are used + * Note! The first four elements are used * by assembler code in head-armv.S */ unsigned int nr; /* architecture number */ - unsigned int __deprecated phys_ram; /* start of physical ram */ unsigned int phys_io; /* start of physical io */ unsigned int io_pg_offst; /* byte offset for io * page tabe entry */ -- cgit v1.2.3-55-g7522 From 110d322b29c08d8cf1dba599fd45ad2b9752a4bb Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 20 Mar 2006 17:10:02 +0000 Subject: [ARM] 3327/1: S3C2410 - add osiris machine support Patch from Ben Dooks Support for Simtec IM2440D20 CPU modules (Osiris) Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/Kconfig | 7 + arch/arm/mach-s3c2410/Makefile | 1 + arch/arm/mach-s3c2410/mach-osiris.c | 290 +++++++++++++++++++++++++++++ include/asm-arm/arch-s3c2410/osiris-cpld.h | 25 +++ include/asm-arm/arch-s3c2410/osiris-map.h | 41 ++++ 5 files changed, 364 insertions(+) create mode 100644 arch/arm/mach-s3c2410/mach-osiris.c create mode 100644 include/asm-arm/arch-s3c2410/osiris-cpld.h create mode 100644 include/asm-arm/arch-s3c2410/osiris-map.h (limited to 'include') diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 0b9d7ca49ec1..ed07c4149d82 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -9,6 +9,13 @@ config MACH_ANUBIS Say Y gere if you are using the Simtec Electronics ANUBIS development system +config MACH_OSIRIS + bool "Simtec IM2440D20 (OSIRIS) module" + select CPU_S3C2440 + help + Say Y here if you are using the Simtec IM2440D20 module, also + known as the Osiris. + config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" select CPU_S3C2410 diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 1217bf00309c..1b3b476e5637 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o # machine specific support obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o +obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o obj-$(CONFIG_ARCH_H1940) += mach-h1940.o obj-$(CONFIG_MACH_N30) += mach-n30.o diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c new file mode 100644 index 000000000000..72083e645e77 --- /dev/null +++ b/arch/arm/mach-s3c2410/mach-osiris.c @@ -0,0 +1,290 @@ +/* linux/arch/arm/mach-s3c2410/mach-osiris.c + * + * Copyright (c) 2005 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "clock.h" +#include "devs.h" +#include "cpu.h" + +/* onboard perihpheral map */ + +static struct map_desc osiris_iodesc[] __initdata = { + /* ISA IO areas (may be over-written later) */ + + { + .virtual = (u32)S3C24XX_VA_ISA_BYTE, + .pfn = __phys_to_pfn(S3C2410_CS5), + .length = SZ_16M, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_WORD, + .pfn = __phys_to_pfn(S3C2410_CS5), + .length = SZ_16M, + .type = MT_DEVICE, + }, + + /* CPLD control registers */ + + { + .virtual = (u32)OSIRIS_VA_CTRL1, + .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1), + .length = SZ_16K, + .type = MT_DEVICE + }, { + .virtual = (u32)OSIRIS_VA_CTRL2, + .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2), + .length = SZ_16K, + .type = MT_DEVICE + }, +}; + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = { + [0] = { + .name = "uclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, + [1] = { + .name = "pclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0. + } +}; + + +static struct s3c2410_uartcfg osiris_uartcfgs[] = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = osiris_serial_clocks, + .clocks_size = ARRAY_SIZE(osiris_serial_clocks) + }, + [1] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = osiris_serial_clocks, + .clocks_size = ARRAY_SIZE(osiris_serial_clocks) + }, +}; + +/* NAND Flash on Osiris board */ + +static int external_map[] = { 2 }; +static int chip0_map[] = { 0 }; +static int chip1_map[] = { 1 }; + +struct mtd_partition osiris_default_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_16K, + .offset = 0 + }, + [1] = { + .name = "/boot", + .size = SZ_4M - SZ_16K, + .offset = SZ_16K, + }, + [2] = { + .name = "user1", + .offset = SZ_4M, + .size = SZ_32M - SZ_4M, + }, + [3] = { + .name = "user2", + .offset = SZ_32M, + .size = MTDPART_SIZ_FULL, + } +}; + +/* the Osiris has 3 selectable slots for nand-flash, the two + * on-board chip areas, as well as the external slot. + * + * Note, there is no current hot-plug support for the External + * socket. +*/ + +static struct s3c2410_nand_set osiris_nand_sets[] = { + [1] = { + .name = "External", + .nr_chips = 1, + .nr_map = external_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part + }, + [0] = { + .name = "chip0", + .nr_chips = 1, + .nr_map = chip0_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part + }, + [2] = { + .name = "chip1", + .nr_chips = 1, + .nr_map = chip1_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part + }, +}; + +static void osiris_nand_select(struct s3c2410_nand_set *set, int slot) +{ + unsigned int tmp; + + slot = set->nr_map[slot] & 3; + + pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n", + slot, set, set->nr_map); + + tmp = __raw_readb(OSIRIS_VA_CTRL1); + tmp &= ~OSIRIS_CTRL1_NANDSEL; + tmp |= slot; + + pr_debug("osiris_nand: ctrl1 now %02x\n", tmp); + + __raw_writeb(tmp, OSIRIS_VA_CTRL1); +} + +static struct s3c2410_platform_nand osiris_nand_info = { + .tacls = 25, + .twrph0 = 60, + .twrph1 = 60, + .nr_sets = ARRAY_SIZE(osiris_nand_sets), + .sets = osiris_nand_sets, + .select_chip = osiris_nand_select, +}; + +/* PCMCIA control and configuration */ + +static struct resource osiris_pcmcia_resource[] = { + [0] = { + .start = 0x0f000000, + .end = 0x0f100000, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0x0c000000, + .end = 0x0c100000, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device osiris_pcmcia = { + .name = "osiris-pcmcia", + .id = -1, + .num_resources = ARRAY_SIZE(osiris_pcmcia_resource), + .resource = osiris_pcmcia_resource, +}; + +/* Standard Osiris devices */ + +static struct platform_device *osiris_devices[] __initdata = { + &s3c_device_i2c, + &s3c_device_nand, + &osiris_pcmcia, +}; + +static struct clk *osiris_clocks[] = { + &s3c24xx_dclk0, + &s3c24xx_dclk1, + &s3c24xx_clkout0, + &s3c24xx_clkout1, + &s3c24xx_uclk, +}; + +static struct s3c24xx_board osiris_board __initdata = { + .devices = osiris_devices, + .devices_count = ARRAY_SIZE(osiris_devices), + .clocks = osiris_clocks, + .clocks_count = ARRAY_SIZE(osiris_clocks) +}; + +void __init osiris_map_io(void) +{ + /* initialise the clocks */ + + s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.rate = 12*1000*1000; + + s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.rate = 24*1000*1000; + + s3c24xx_clkout0.parent = &s3c24xx_dclk0; + s3c24xx_clkout1.parent = &s3c24xx_dclk1; + + s3c24xx_uclk.parent = &s3c24xx_clkout1; + + s3c_device_nand.dev.platform_data = &osiris_nand_info; + + s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); + s3c24xx_init_clocks(0); + s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); + s3c24xx_set_board(&osiris_board); + + /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ + __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON); + + /* write-protect line to the NAND */ + s3c2410_gpio_setpin(S3C2410_GPA0, 1); +} + +MACHINE_START(OSIRIS, "Simtec-OSIRIS") + /* Maintainer: Ben Dooks */ + .phys_ram = S3C2410_SDRAM_PA, + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = osiris_map_io, + .init_irq = s3c24xx_init_irq, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/include/asm-arm/arch-s3c2410/osiris-cpld.h b/include/asm-arm/arch-s3c2410/osiris-cpld.h new file mode 100644 index 000000000000..e9d1ae1f354f --- /dev/null +++ b/include/asm-arm/arch-s3c2410/osiris-cpld.h @@ -0,0 +1,25 @@ +/* linux/include/asm-arm/arch-s3c2410/osiris-cpld.h + * + * (c) 2005 Simtec Electronics + * http://www.simtec.co.uk/products/ + * Ben Dooks + * + * OSIRIS - CPLD control constants + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_OSIRISCPLD_H +#define __ASM_ARCH_OSIRISCPLD_H + +/* CTRL1 - NAND WP control */ + +#define OSIRIS_CTRL1_NANDSEL (0x3) +#define OSIRIS_CTRL1_BOOT_INT (1<<3) +#define OSIRIS_CTRL1_PCMCIA (1<<4) +#define OSIRIS_CTRL1_PCMCIA_nWAIT (1<<6) +#define OSIRIS_CTRL1_PCMCIA_nIOIS16 (1<<7) + +#endif /* __ASM_ARCH_OSIRISCPLD_H */ diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h new file mode 100644 index 000000000000..7c4b0cd2d14d --- /dev/null +++ b/include/asm-arm/arch-s3c2410/osiris-map.h @@ -0,0 +1,41 @@ +/* linux/include/asm-arm/arch-s3c2410/osiris-map.h + * + * (c) 2005 Simtec Electronics + * http://www.simtec.co.uk/products/ + * Ben Dooks + * + * OSIRIS - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: +*/ + +/* needs arch/map.h including with this */ + +#ifndef __ASM_ARCH_OSIRISMAP_H +#define __ASM_ARCH_OSIRISMAP_H + +/* start peripherals off after the S3C2410 */ + +#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x05000000)) + +#define OSIRIS_PA_CPLD (S3C2410_CS1 | (3<<25)) + +/* we put the CPLD registers next, to get them out of the way */ + +#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) /* 0x01300000 */ +#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD) + +#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) /* 0x01400000 */ +#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<24)) + +#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) /* 0x01500000 */ +#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<24)) + +#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) /* 0x01600000 */ +#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<24)) + +#endif /* __ASM_ARCH_OSIRISMAP_H */ -- cgit v1.2.3-55-g7522 From 3fc3e1c0640887f883c28330e9d35145d23b2696 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 20 Mar 2006 17:10:07 +0000 Subject: [ARM] 3333/1: S3C2XX - add dclk and clkout clock support Patch from Ben Dooks Add enable and set_parent calls for the dclk and clkout clocks. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/clock.c | 94 +++++++++++++++++++++++++++++++- include/asm-arm/arch-s3c2410/regs-gpio.h | 2 + 2 files changed, 95 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index 773b7aec3e99..e205a6316b08 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -45,6 +45,7 @@ #include #include +#include #include "clock.h" #include "cpu.h" @@ -285,24 +286,115 @@ static struct clk clk_p = { /* clocks that could be registered by external code */ +static int s3c24xx_dclk_enable(struct clk *clk, int enable) +{ + unsigned long dclkcon = __raw_readl(S3C2410_DCLKCON); + + if (enable) + dclkcon |= clk->ctrlbit; + else + dclkcon &= ~clk->ctrlbit; + + __raw_writel(dclkcon, S3C2410_DCLKCON); + + return 0; +} + +static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) +{ + unsigned long dclkcon; + unsigned int uclk; + + if (parent == &clk_upll) + uclk = 1; + else if (parent == &clk_p) + uclk = 0; + else + return -EINVAL; + + clk->parent = parent; + + dclkcon = __raw_readl(S3C2410_DCLKCON); + + if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { + if (uclk) + dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; + else + dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; + } else { + if (uclk) + dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; + else + dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; + } + + __raw_writel(dclkcon, S3C2410_DCLKCON); + + return 0; +} + + +static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) +{ + unsigned long mask; + unsigned long source; + + /* calculate the MISCCR setting for the clock */ + + if (parent == &clk_xtal) + source = S3C2410_MISCCR_CLK0_MPLL; + else if (parent == &clk_upll) + source = S3C2410_MISCCR_CLK0_UPLL; + else if (parent == &clk_f) + source = S3C2410_MISCCR_CLK0_FCLK; + else if (parent == &clk_p) + source = S3C2410_MISCCR_CLK0_PCLK; + else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) + source = S3C2410_MISCCR_CLK0_DCLK0; + else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) + source = S3C2410_MISCCR_CLK0_DCLK0; + else + return -EINVAL; + + if (clk == &s3c24xx_dclk0) + mask = S3C2410_MISCCR_CLK0_MASK; + else { + source <<= 4; + mask = S3C2410_MISCCR_CLK1_MASK; + } + + s3c2410_modify_misccr(mask, source); + return 0; +} + +/* external clock definitions */ + struct clk s3c24xx_dclk0 = { .name = "dclk0", .id = -1, + .ctrlbit = S3C2410_DCLKCON_DCLK0EN, + .enable = s3c24xx_dclk_enable, + .set_parent = s3c24xx_dclk_setparent, }; struct clk s3c24xx_dclk1 = { .name = "dclk1", .id = -1, + .ctrlbit = S3C2410_DCLKCON_DCLK0EN, + .enable = s3c24xx_dclk_enable, + .set_parent = s3c24xx_dclk_setparent, }; struct clk s3c24xx_clkout0 = { .name = "clkout0", .id = -1, + .set_parent = s3c24xx_clkout_setparent, }; struct clk s3c24xx_clkout1 = { .name = "clkout1", .id = -1, + .set_parent = s3c24xx_clkout_setparent, }; struct clk s3c24xx_uclk = { @@ -423,7 +515,7 @@ int s3c24xx_register_clock(struct clk *clk) /* if this is a standard clock, set the usage state */ - if (clk->ctrlbit) { + if (clk->ctrlbit && clk->enable == s3c24xx_clkcon_enable) { unsigned long clkcon = __raw_readl(S3C2410_CLKCON); clk->usage = (clkcon & clk->ctrlbit) ? 1 : 0; diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index 9697f93afe74..d2574084697f 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h @@ -979,6 +979,7 @@ #define S3C2410_MISCCR_CLK0_HCLK (3<<4) #define S3C2410_MISCCR_CLK0_PCLK (4<<4) #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) +#define S3C2410_MISCCR_CLK0_MASK (7<<4) #define S3C2410_MISCCR_CLK1_MPLL (0<<8) #define S3C2410_MISCCR_CLK1_UPLL (1<<8) @@ -986,6 +987,7 @@ #define S3C2410_MISCCR_CLK1_HCLK (3<<8) #define S3C2410_MISCCR_CLK1_PCLK (4<<8) #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) +#define S3C2410_MISCCR_CLK1_MASK (7<<8) #define S3C2410_MISCCR_USBSUSPND0 (1<<12) #define S3C2410_MISCCR_USBSUSPND1 (1<<13) -- cgit v1.2.3-55-g7522 From 0328ad23cfd8a0501f44a1b83e49d5b0e47e2b3c Mon Sep 17 00:00:00 2001 From: Deepak Saxena Date: Mon, 20 Mar 2006 17:10:08 +0000 Subject: [ARM] 3334/1: Add support for IXDP28x5 platforms Patch from Deepak Saxena This patch adds support for Intel's IXDP28x5 platform. This is just and IXDP2801 with a new CPU rev but the bootloader has been updated to reflect a new machine ID so we just build support for it by default when we build IXDP2801. Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- arch/arm/mach-ixp2000/Kconfig | 9 +++++++-- arch/arm/mach-ixp2000/ixdp2x01.c | 20 ++++++++++++++++++-- include/asm-arm/arch-ixp2000/system.h | 2 +- 3 files changed, 26 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-ixp2000/Kconfig b/arch/arm/mach-ixp2000/Kconfig index ecb58d83478e..86f53f8ccbf5 100644 --- a/arch/arm/mach-ixp2000/Kconfig +++ b/arch/arm/mach-ixp2000/Kconfig @@ -43,12 +43,17 @@ config ARCH_IXDP2401 this platform, see . config ARCH_IXDP2801 - bool "Support Intel IXDP2801" + bool "Support Intel IXDP2801 and IXDP28x5" help Say 'Y' here if you want your kernel to support the Intel - IXDP2801 reference platform. For more information on + IXDP2801/2805/2855 reference platforms. For more information on this platform, see . +config MACH_IXDP28X5 + bool + depends on ARCH_IXDP2801 + default y + config ARCH_IXDP2X01 bool depends on ARCH_IXDP2401 || ARCH_IXDP2801 diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 150519fb38ec..f9d4968c1d66 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -284,7 +284,7 @@ static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys) { sys->mem_offset = 0xe0000000; - if (machine_is_ixdp2801()) + if (machine_is_ixdp2801() || machine_is_ixdp28x5()) sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16); return ixp2000_pci_setup(nr, sys); @@ -300,7 +300,8 @@ struct hw_pci ixdp2x01_pci __initdata = { int __init ixdp2x01_pci_init(void) { - if (machine_is_ixdp2401() || machine_is_ixdp2801()) + if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\ + machine_is_ixdp28x5()) pci_common_init(&ixdp2x01_pci); return 0; @@ -400,6 +401,21 @@ MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform") .timer = &ixdp2x01_timer, .init_machine = ixdp2x01_init_machine, MACHINE_END + +/* + * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel + * changed the machine ID in the bootloader + */ +MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform") + /* Maintainer: MontaVista Software, Inc. */ + .phys_io = IXP2000_UART_PHYS_BASE, + .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = ixdp2x01_map_io, + .init_irq = ixdp2x01_init_irq, + .timer = &ixdp2x01_timer, + .init_machine = ixdp2x01_init_machine, +MACHINE_END #endif diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h index ddbbb34b5f95..3cc9a04f68cb 100644 --- a/include/asm-arm/arch-ixp2000/system.h +++ b/include/asm-arm/arch-ixp2000/system.h @@ -37,7 +37,7 @@ static inline void arch_reset(char mode) * to cause a complete reset of the CPU and all external devices * and move the flash bank register back to 0. */ - if (machine_is_ixdp2801()) { + if (machine_is_ixdp2801() || machine_is_ixdp28x5()) { unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); -- cgit v1.2.3-55-g7522 From 6d4518d76f9612d580f9423cc0c3364a06b69588 Mon Sep 17 00:00:00 2001 From: Peter Teichmann Date: Mon, 20 Mar 2006 17:10:09 +0000 Subject: [ARM] 3346/1: Fix udelay() for HZ values different from 100 Patch from Peter Teichmann Currently, if the kernels HZ value is greater than 100, delays with the udelay function are too short. This can cause trouble for instance with the zd1201 usb wlan driver. This patch suggests a solution that keeps the overhead small and maintains (hopefully) sufficient resolution. Signed-off-by: Peter Teichmann Signed-off-by: Russell King --- arch/arm/lib/delay.S | 20 ++++++++++++-------- include/asm-arm/delay.h | 12 +++++++----- 2 files changed, 19 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/arch/arm/lib/delay.S b/arch/arm/lib/delay.S index b3fb475b4120..9183b06c0e2f 100644 --- a/arch/arm/lib/delay.S +++ b/arch/arm/lib/delay.S @@ -9,28 +9,32 @@ */ #include #include +#include .text .LC0: .word loops_per_jiffy +.LC1: .word (2199023*HZ)>>11 /* - * 0 <= r0 <= 2000 + * r0 <= 2000 + * lpj <= 0x01ffffff (max. 3355 bogomips) + * HZ <= 1000 */ + ENTRY(__udelay) - mov r2, #0x6800 - orr r2, r2, #0x00db + ldr r2, .LC1 mul r0, r2, r0 -ENTRY(__const_udelay) @ 0 <= r0 <= 0x01ffffff +ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06 ldr r2, .LC0 - ldr r2, [r2] @ max = 0x0fffffff - mov r0, r0, lsr #11 @ max = 0x00003fff - mov r2, r2, lsr #11 @ max = 0x0003ffff + ldr r2, [r2] @ max = 0x01ffffff + mov r0, r0, lsr #14 @ max = 0x0001ffff + mov r2, r2, lsr #10 @ max = 0x00007fff mul r0, r2, r0 @ max = 2^32-1 movs r0, r0, lsr #6 RETINSTR(moveq,pc,lr) /* - * loops = (r0 * 0x10c6 * 100 * loops_per_jiffy) / 2^32 + * loops = r0 * HZ * loops_per_jiffy / 1000000 * * Oh, if only we had a cycle counter... */ diff --git a/include/asm-arm/delay.h b/include/asm-arm/delay.h index 1704360e9699..b2deda181549 100644 --- a/include/asm-arm/delay.h +++ b/include/asm-arm/delay.h @@ -6,6 +6,8 @@ #ifndef __ASM_ARM_DELAY_H #define __ASM_ARM_DELAY_H +#include /* HZ */ + extern void __delay(int loops); /* @@ -13,7 +15,7 @@ extern void __delay(int loops); * it, it means that you're calling udelay() with an out of range value. * * With currently imposed limits, this means that we support a max delay - * of 2000us and 671 bogomips + * of 2000us. Further limits: HZ<=1000 and bogomips<=3355 */ extern void __bad_udelay(void); @@ -32,10 +34,10 @@ extern void __const_udelay(unsigned long); #define MAX_UDELAY_MS 2 -#define udelay(n) \ - (__builtin_constant_p(n) ? \ - ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \ - __const_udelay((n) * 0x68dbul)) : \ +#define udelay(n) \ + (__builtin_constant_p(n) ? \ + ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \ + __const_udelay((n) * ((2199023U*HZ)>>11))) : \ __udelay(n)) #endif /* defined(_ARM_DELAY_H) */ -- cgit v1.2.3-55-g7522 From 03bd14c4b7fa535c78f17751172dbe8937729f05 Mon Sep 17 00:00:00 2001 From: Alessandro Zummo Date: Mon, 20 Mar 2006 17:10:10 +0000 Subject: [ARM] 3349/1: ixp4xx exp bus defines Patch from Alessandro Zummo This patch adds a few defines that are useful to configure the CS regions on ixp4xx. Signed-off-by: Alessandro Zummo Signed-off-by: OEyvind Repvik Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/platform.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h index daf9790645ca..13aee17b0475 100644 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ b/include/asm-arm/arch-ixp4xx/platform.h @@ -38,6 +38,33 @@ extern unsigned long ixp4xx_exp_bus_size; #define IXP4XX_EXP_BUS_BASE(region)\ (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size)) +#define IXP4XX_EXP_BUS_END(region)\ + (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1) + +/* Those macros can be used to adjust timing and configure + * other features for each region. + */ + +#define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16) +#define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20) +#define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22) +#define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26) +#define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28) +#define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10) +#define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14) + +#define IXP4XX_EXP_BUS_CS_EN (1L << 31) +#define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6) +#define IXP4XX_EXP_BUS_HRDY_POL (1L << 5) +#define IXP4XX_EXP_BUS_MUX_EN (1L << 4) +#define IXP4XX_EXP_BUS_SPLT_EN (1L << 3) +#define IXP4XX_EXP_BUS_WR_EN (1L << 1) +#define IXP4XX_EXP_BUS_BYTE_EN (1L << 0) + +#define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00 +#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01 +#define IXP4XX_EXP_BUS_CYCLES_HPI 0x02 + #define IXP4XX_FLASH_WRITABLE (0x2) #define IXP4XX_FLASH_DEFAULT (0xbcd23c40) #define IXP4XX_FLASH_WRITE (0xbcd23c42) -- cgit v1.2.3-55-g7522 From e7736d47a11a771ba87314be563b2cb6b8d11d14 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 20 Mar 2006 17:10:13 +0000 Subject: [ARM] 3369/1: ep93xx: add core cirrus ep93xx support Patch from Lennert Buytenhek This patch adds support for the Cirrus ep93xx series of CPUs. The ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs, IrDA, MaverickCrunch floating point coprocessor, between 24 and 64 GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster engine, graphics accelerator, IDE controller and a bunch of other stuff. This patch adds the core ep93xx support code, and support for the Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/Kconfig | 9 ++ arch/arm/Makefile | 1 + arch/arm/mach-ep93xx/Kconfig | 21 ++++ arch/arm/mach-ep93xx/Makefile | 10 ++ arch/arm/mach-ep93xx/Makefile.boot | 2 + arch/arm/mach-ep93xx/core.c | 173 ++++++++++++++++++++++++++++++ arch/arm/mach-ep93xx/gesbc9312.c | 40 +++++++ arch/arm/mach-ep93xx/ts72xx.c | 118 ++++++++++++++++++++ arch/arm/mm/Kconfig | 2 +- include/asm-arm/arch-ep93xx/debug-macro.S | 22 ++++ include/asm-arm/arch-ep93xx/dma.h | 3 + include/asm-arm/arch-ep93xx/entry-macro.S | 53 +++++++++ include/asm-arm/arch-ep93xx/ep93xx-regs.h | 114 ++++++++++++++++++++ include/asm-arm/arch-ep93xx/gesbc9312.h | 3 + include/asm-arm/arch-ep93xx/hardware.h | 12 +++ include/asm-arm/arch-ep93xx/io.h | 8 ++ include/asm-arm/arch-ep93xx/irqs.h | 78 ++++++++++++++ include/asm-arm/arch-ep93xx/memory.h | 14 +++ include/asm-arm/arch-ep93xx/platform.h | 14 +++ include/asm-arm/arch-ep93xx/system.h | 26 +++++ include/asm-arm/arch-ep93xx/timex.h | 5 + include/asm-arm/arch-ep93xx/ts72xx.h | 90 ++++++++++++++++ include/asm-arm/arch-ep93xx/uncompress.h | 53 +++++++++ include/asm-arm/arch-ep93xx/vmalloc.h | 5 + 24 files changed, 875 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-ep93xx/Kconfig create mode 100644 arch/arm/mach-ep93xx/Makefile create mode 100644 arch/arm/mach-ep93xx/Makefile.boot create mode 100644 arch/arm/mach-ep93xx/core.c create mode 100644 arch/arm/mach-ep93xx/gesbc9312.c create mode 100644 arch/arm/mach-ep93xx/ts72xx.c create mode 100644 include/asm-arm/arch-ep93xx/debug-macro.S create mode 100644 include/asm-arm/arch-ep93xx/dma.h create mode 100644 include/asm-arm/arch-ep93xx/entry-macro.S create mode 100644 include/asm-arm/arch-ep93xx/ep93xx-regs.h create mode 100644 include/asm-arm/arch-ep93xx/gesbc9312.h create mode 100644 include/asm-arm/arch-ep93xx/hardware.h create mode 100644 include/asm-arm/arch-ep93xx/io.h create mode 100644 include/asm-arm/arch-ep93xx/irqs.h create mode 100644 include/asm-arm/arch-ep93xx/memory.h create mode 100644 include/asm-arm/arch-ep93xx/platform.h create mode 100644 include/asm-arm/arch-ep93xx/system.h create mode 100644 include/asm-arm/arch-ep93xx/timex.h create mode 100644 include/asm-arm/arch-ep93xx/ts72xx.h create mode 100644 include/asm-arm/arch-ep93xx/uncompress.h create mode 100644 include/asm-arm/arch-ep93xx/vmalloc.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6e9e8cedd723..0dd24ebdf6ac 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -108,6 +108,13 @@ config ARCH_EBSA110 Ethernet interface, two PCMCIA sockets, two serial ports and a parallel port. +config ARCH_EP93XX + bool "EP93xx-based" + select ARM_AMBA + select ARM_VIC + help + This enables support for the Cirrus EP93xx series of CPUs. + config ARCH_FOOTBRIDGE bool "FootBridge" select FOOTBRIDGE @@ -250,6 +257,8 @@ endchoice source "arch/arm/mach-clps711x/Kconfig" +source "arch/arm/mach-ep93xx/Kconfig" + source "arch/arm/mach-footbridge/Kconfig" source "arch/arm/mach-integrator/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index fbfc14a56b96..b5b1e4087516 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -105,6 +105,7 @@ endif machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200 + machine-$(CONFIG_ARCH_EP93XX) := ep93xx ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig new file mode 100644 index 000000000000..cec5a21ca4e3 --- /dev/null +++ b/arch/arm/mach-ep93xx/Kconfig @@ -0,0 +1,21 @@ +if ARCH_EP93XX + +menu "Cirrus EP93xx Implementation Options" + +comment "EP93xx Platforms" + +config MACH_GESBC9312 + bool "Support Glomation GESBC-9312-sx" + help + Say 'Y' here if you want your kernel to support the Glomation + GESBC-9312-sx board. + +config MACH_TS72XX + bool "Support Technologic Systems TS-72xx SBC" + help + Say 'Y' here if you want your kernel to support the + Technologic Systems TS-72xx board. + +endmenu + +endif diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile new file mode 100644 index 000000000000..5393af989e94 --- /dev/null +++ b/arch/arm/mach-ep93xx/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the linux kernel. +# +obj-y := core.o +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o +obj-$(CONFIG_MACH_TS72XX) += ts72xx.o diff --git a/arch/arm/mach-ep93xx/Makefile.boot b/arch/arm/mach-ep93xx/Makefile.boot new file mode 100644 index 000000000000..d5561ad15bad --- /dev/null +++ b/arch/arm/mach-ep93xx/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c new file mode 100644 index 000000000000..f831f74dc8cc --- /dev/null +++ b/arch/arm/mach-ep93xx/core.c @@ -0,0 +1,173 @@ +/* + * arch/arm/mach-ep93xx/core.c + * Core routines for Cirrus EP93xx chips. + * + * Copyright (C) 2006 Lennert Buytenhek + * + * Thanks go to Michael Burian and Ray Lehtiniemi for their key + * role in the ep93xx linux community. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + + +/************************************************************************* + * Static I/O mappings that are needed for all EP93xx platforms + *************************************************************************/ +static struct map_desc ep93xx_io_desc[] __initdata = { + { + .virtual = EP93XX_AHB_VIRT_BASE, + .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE), + .length = EP93XX_AHB_SIZE, + .type = MT_DEVICE, + }, { + .virtual = EP93XX_APB_VIRT_BASE, + .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE), + .length = EP93XX_APB_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init ep93xx_map_io(void) +{ + iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); +} + + +/************************************************************************* + * Timer handling for EP93xx + ************************************************************************* + * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and + * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate + * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, + * is free-running, and can't generate interrupts. + * + * The 508 kHz timers are ideal for use for the timer interrupt, as the + * most common values of HZ divide 508 kHz nicely. We pick one of the 16 + * bit timers (timer 1) since we don't need more than 16 bits of reload + * value as long as HZ >= 8. + * + * The higher clock rate of timer 4 makes it a better choice than the + * other timers for use in gettimeoffset(), while the fact that it can't + * generate interrupts means we don't have to worry about not being able + * to use this timer for something else. We also use timer 4 for keeping + * track of lost jiffies. + */ +static unsigned int last_jiffy_time; + +#define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) + +static int ep93xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + write_seqlock(&xtime_lock); + + __raw_writel(1, EP93XX_TIMER1_CLEAR); + while (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time + >= TIMER4_TICKS_PER_JIFFY) { + last_jiffy_time += TIMER4_TICKS_PER_JIFFY; + timer_tick(regs); + } + + write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; +} + +static struct irqaction ep93xx_timer_irq = { + .name = "ep93xx timer", + .flags = SA_INTERRUPT | SA_TIMER, + .handler = ep93xx_timer_interrupt, +}; + +static void __init ep93xx_timer_init(void) +{ + /* Enable periodic HZ timer. */ + __raw_writel(0x48, EP93XX_TIMER1_CONTROL); + __raw_writel((508000 / HZ) - 1, EP93XX_TIMER1_LOAD); + __raw_writel(0xc8, EP93XX_TIMER1_CONTROL); + + /* Enable lost jiffy timer. */ + __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH); + + setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); +} + +static unsigned long ep93xx_gettimeoffset(void) +{ + int offset; + + offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; + + /* Calculate (1000000 / 983040) * offset. */ + return offset + (53 * offset / 3072); +} + +struct sys_timer ep93xx_timer = { + .init = ep93xx_timer_init, + .offset = ep93xx_gettimeoffset, +}; + + +/************************************************************************* + * EP93xx IRQ handling + *************************************************************************/ +void __init ep93xx_init_irq(void) +{ + vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK); + vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK); +} + + +/************************************************************************* + * EP93xx peripheral handling + *************************************************************************/ +void __init ep93xx_init_devices(void) +{ + unsigned int v; + + /* + * Disallow access to MaverickCrunch initially. + */ + v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG); + v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE; + __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); + __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG); +} diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c new file mode 100644 index 000000000000..d18fcb1a2f1b --- /dev/null +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-ep93xx/gesbc9312.c + * Glomation GESBC-9312-sx support. + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void __init gesbc9312_init_machine(void) +{ + ep93xx_init_devices(); + physmap_configure(0x60000000, 0x00800000, 4, NULL); +} + +MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") + /* Maintainer: Lennert Buytenhek */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = gesbc9312_init_machine, +MACHINE_END diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c new file mode 100644 index 000000000000..777e75daa8a5 --- /dev/null +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -0,0 +1,118 @@ +/* + * arch/arm/mach-ep93xx/ts72xx.c + * Technologic Systems TS72xx SBC support. + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct map_desc ts72xx_io_desc[] __initdata = { + { + .virtual = TS72XX_MODEL_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_MODEL_PHYS_BASE), + .length = TS72XX_MODEL_SIZE, + .type = MT_DEVICE, + }, { + .virtual = TS72XX_OPTIONS_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE), + .length = TS72XX_OPTIONS_SIZE, + .type = MT_DEVICE, + }, { + .virtual = TS72XX_OPTIONS2_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE), + .length = TS72XX_OPTIONS2_SIZE, + .type = MT_DEVICE, + } +}; + +static struct map_desc ts72xx_nand_io_desc[] __initdata = { + { + .virtual = TS72XX_NAND_DATA_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_NAND1_DATA_PHYS_BASE), + .length = TS72XX_NAND_DATA_SIZE, + .type = MT_DEVICE, + }, { + .virtual = TS72XX_NAND_CONTROL_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_NAND1_CONTROL_PHYS_BASE), + .length = TS72XX_NAND_CONTROL_SIZE, + .type = MT_DEVICE, + }, { + .virtual = TS72XX_NAND_BUSY_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_NAND1_BUSY_PHYS_BASE), + .length = TS72XX_NAND_BUSY_SIZE, + .type = MT_DEVICE, + } +}; + +static struct map_desc ts72xx_alternate_nand_io_desc[] __initdata = { + { + .virtual = TS72XX_NAND_DATA_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_NAND2_DATA_PHYS_BASE), + .length = TS72XX_NAND_DATA_SIZE, + .type = MT_DEVICE, + }, { + .virtual = TS72XX_NAND_CONTROL_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_NAND2_CONTROL_PHYS_BASE), + .length = TS72XX_NAND_CONTROL_SIZE, + .type = MT_DEVICE, + }, { + .virtual = TS72XX_NAND_BUSY_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_NAND2_BUSY_PHYS_BASE), + .length = TS72XX_NAND_BUSY_SIZE, + .type = MT_DEVICE, + } +}; + +static void __init ts72xx_map_io(void) +{ + ep93xx_map_io(); + iotable_init(ts72xx_io_desc, ARRAY_SIZE(ts72xx_io_desc)); + + /* + * The TS-7200 has NOR flash, the other models have NAND flash. + */ + if (!board_is_ts7200()) { + if (is_ts9420_installed()) { + iotable_init(ts72xx_alternate_nand_io_desc, + ARRAY_SIZE(ts72xx_alternate_nand_io_desc)); + } else { + iotable_init(ts72xx_nand_io_desc, + ARRAY_SIZE(ts72xx_nand_io_desc)); + } + } +} + +static void __init ts72xx_init_machine(void) +{ + ep93xx_init_devices(); + if (board_is_ts7200()) + physmap_configure(TS72XX_NOR_PHYS_BASE, 0x01000000, 1, NULL); +} + +MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") + /* Maintainer: Lennert Buytenhek */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = ts72xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = ts72xx_init_machine, +MACHINE_END diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 3b79d0e23455..eaaec90db972 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -62,7 +62,7 @@ config CPU_ARM720T # ARM920T config CPU_ARM920T bool "Support ARM920T processor" if !ARCH_S3C2410 - depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 + depends on ARCH_EP93XX || ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 default y if ARCH_S3C2410 || ARCH_AT91RM9200 select CPU_32v4 select CPU_ABRT_EV4T diff --git a/include/asm-arm/arch-ep93xx/debug-macro.S b/include/asm-arm/arch-ep93xx/debug-macro.S new file mode 100644 index 000000000000..397565a0c671 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/debug-macro.S @@ -0,0 +1,22 @@ +/* + * linux/include/asm-arm/arch-ep93xx/debug-macro.S + * Debugging macro include header + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ +#include + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =EP93XX_APB_PHYS_BASE @ Physical base + ldrne \rx, =EP93XX_APB_VIRT_BASE @ virtual base + orr \rx, \rx, #0x000c0000 + .endm + +#include diff --git a/include/asm-arm/arch-ep93xx/dma.h b/include/asm-arm/arch-ep93xx/dma.h new file mode 100644 index 000000000000..898b3ab7fd46 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/dma.h @@ -0,0 +1,3 @@ +/* + * linux/include/asm-arm/arch-ep93xx/dma.h + */ diff --git a/include/asm-arm/arch-ep93xx/entry-macro.S b/include/asm-arm/arch-ep93xx/entry-macro.S new file mode 100644 index 000000000000..84140a28dfcf --- /dev/null +++ b/include/asm-arm/arch-ep93xx/entry-macro.S @@ -0,0 +1,53 @@ +/* + * linux/include/asm-arm/arch-ep93xx/entry-macro.S + * IRQ demultiplexing for EP93xx + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =(EP93XX_AHB_VIRT_BASE) + orr \base, \base, #0x000b0000 + mov \irqnr, #0 + ldr \irqstat, [\base] @ lower 32 interrupts + cmp \irqstat, #0 + bne 1001f + + eor \base, \base, #0x00070000 + ldr \irqstat, [\base] @ upper 32 interrupts + cmp \irqstat, #0 + beq 1002f + mov \irqnr, #0x20 + +1001: + movs \tmp, \irqstat, lsl #16 + movne \irqstat, \tmp + addeq \irqnr, \irqnr, #16 + + movs \tmp, \irqstat, lsl #8 + movne \irqstat, \tmp + addeq \irqnr, \irqnr, #8 + + movs \tmp, \irqstat, lsl #4 + movne \irqstat, \tmp + addeq \irqnr, \irqnr, #4 + + movs \tmp, \irqstat, lsl #2 + movne \irqstat, \tmp + addeq \irqnr, \irqnr, #2 + + movs \tmp, \irqstat, lsl #1 + addeq \irqnr, \irqnr, #1 + orrs \base, \base, #1 + +1002: + .endm diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h new file mode 100644 index 000000000000..693f23886e85 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/ep93xx-regs.h @@ -0,0 +1,114 @@ +/* + * linux/include/asm-arm/arch-ep93xx/ep93xx-regs.h + */ + +#ifndef __ASM_ARCH_EP93XX_REGS_H +#define __ASM_ARCH_EP93XX_REGS_H + +/* + * EP93xx linux memory map: + * + * virt phys size + * fe800000 5M per-platform mappings + * fed00000 80800000 2M APB + * fef00000 80000000 1M AHB + */ + +#define EP93XX_AHB_PHYS_BASE 0x80000000 +#define EP93XX_AHB_VIRT_BASE 0xfef00000 +#define EP93XX_AHB_SIZE 0x00100000 + +#define EP93XX_APB_PHYS_BASE 0x80800000 +#define EP93XX_APB_VIRT_BASE 0xfed00000 +#define EP93XX_APB_SIZE 0x00200000 + + +/* AHB peripherals */ +#define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) + +#define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) + +#define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000) +#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) + +#define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) + +#define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) + +#define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) + +#define EP93XX_PCMCIA_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00080000) + +#define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) + +#define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) + +#define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) + +#define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) + + +/* APB peripherals */ +#define EP93XX_TIMER_BASE (EP93XX_APB_VIRT_BASE + 0x00010000) +#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) +#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) +#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) +#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) +#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) +#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) +#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) +#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) +#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) +#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) +#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) +#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) +#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) +#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) +#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) + +#define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000) + +#define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) + +#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) + +#define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) + +#define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000) + +#define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000) + +#define EP93XX_UART1_BASE (EP93XX_APB_VIRT_BASE + 0x000c0000) +#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000) + +#define EP93XX_UART2_BASE (EP93XX_APB_VIRT_BASE + 0x000d0000) +#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000) + +#define EP93XX_UART3_BASE (EP93XX_APB_VIRT_BASE + 0x000e0000) +#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000) + +#define EP93XX_KEY_MATRIX_BASE (EP93XX_APB_VIRT_BASE + 0x000f0000) + +#define EP93XX_ADC_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) +#define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) + +#define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) + +#define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) + +#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) +#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) +#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) +#define EP93XX_SYSCON_CLOCK_CONTROL EP93XX_SYSCON_REG(0x04) +#define EP93XX_SYSCON_CLOCK_UARTBAUD 0x20000000 +#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 +#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) +#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) +#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) +#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 +#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) + +#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) + + +#endif diff --git a/include/asm-arm/arch-ep93xx/gesbc9312.h b/include/asm-arm/arch-ep93xx/gesbc9312.h new file mode 100644 index 000000000000..4d0b3023bff7 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/gesbc9312.h @@ -0,0 +1,3 @@ +/* + * linux/include/asm-arm/arch-ep93xx/gesbc9312.h + */ diff --git a/include/asm-arm/arch-ep93xx/hardware.h b/include/asm-arm/arch-ep93xx/hardware.h new file mode 100644 index 000000000000..9b69f454065d --- /dev/null +++ b/include/asm-arm/arch-ep93xx/hardware.h @@ -0,0 +1,12 @@ +/* + * linux/include/asm-arm/arch-ep93xx/hardware.h + */ + +#include "ep93xx-regs.h" + +#define pcibios_assign_all_busses() 0 + +#include "platform.h" + +#include "gesbc9312.h" +#include "ts72xx.h" diff --git a/include/asm-arm/arch-ep93xx/io.h b/include/asm-arm/arch-ep93xx/io.h new file mode 100644 index 000000000000..7b4d25e29060 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/io.h @@ -0,0 +1,8 @@ +/* + * linux/include/asm-arm/arch-ep93xx/io.h + */ + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(p) ((void __iomem *)(p)) +#define __mem_pci(p) (p) diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h new file mode 100644 index 000000000000..8c10fb964faf --- /dev/null +++ b/include/asm-arm/arch-ep93xx/irqs.h @@ -0,0 +1,78 @@ +/* + * linux/include/asm-arm/arch-ep93xx/irqs.h + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#define IRQ_EP93XX_COMMRX 2 +#define IRQ_EP93XX_COMMTX 3 +#define IRQ_EP93XX_TIMER1 4 +#define IRQ_EP93XX_TIMER2 5 +#define IRQ_EP93XX_AACINTR 6 +#define IRQ_EP93XX_DMAM2P0 7 +#define IRQ_EP93XX_DMAM2P1 8 +#define IRQ_EP93XX_DMAM2P2 9 +#define IRQ_EP93XX_DMAM2P3 10 +#define IRQ_EP93XX_DMAM2P4 11 +#define IRQ_EP93XX_DMAM2P5 12 +#define IRQ_EP93XX_DMAM2P6 13 +#define IRQ_EP93XX_DMAM2P7 14 +#define IRQ_EP93XX_DMAM2P8 15 +#define IRQ_EP93XX_DMAM2P9 16 +#define IRQ_EP93XX_DMAM2M0 17 +#define IRQ_EP93XX_DMAM2M1 18 +#define IRQ_EP93XX_GPIO0MUX 20 +#define IRQ_EP93XX_GPIO1MUX 21 +#define IRQ_EP93XX_GPIO2MUX 22 +#define IRQ_EP93XX_GPIO3MUX 22 +#define IRQ_EP93XX_UART1RX 23 +#define IRQ_EP93XX_UART1TX 24 +#define IRQ_EP93XX_UART2RX 25 +#define IRQ_EP93XX_UART2TX 26 +#define IRQ_EP93XX_UART3RX 27 +#define IRQ_EP93XX_UART3TX 28 +#define IRQ_EP93XX_KEY 29 +#define IRQ_EP93XX_TOUCH 30 +#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc + +#define IRQ_EP93XX_EXT0 32 +#define IRQ_EP93XX_EXT1 33 +#define IRQ_EP93XX_EXT2 34 +#define IRQ_EP93XX_64HZ 35 +#define IRQ_EP93XX_WATCHDOG 36 +#define IRQ_EP93XX_RTC 37 +#define IRQ_EP93XX_IRDA 38 +#define IRQ_EP93XX_ETHERNET 39 +#define IRQ_EP93XX_EXT3 40 +#define IRQ_EP93XX_PROG 41 +#define IRQ_EP93XX_1HZ 42 +#define IRQ_EP93XX_VSYNC 43 +#define IRQ_EP93XX_VIDEO_FIFO 44 +#define IRQ_EP93XX_SSP1RX 45 +#define IRQ_EP93XX_SSP1TX 46 +#define IRQ_EP93XX_GPIO4MUX 47 +#define IRQ_EP93XX_GPIO5MUX 48 +#define IRQ_EP93XX_GPIO6MUX 49 +#define IRQ_EP93XX_GPIO7MUX 50 +#define IRQ_EP93XX_TIMER3 51 +#define IRQ_EP93XX_UART1 52 +#define IRQ_EP93XX_SSP 53 +#define IRQ_EP93XX_UART2 54 +#define IRQ_EP93XX_UART3 55 +#define IRQ_EP93XX_USB 56 +#define IRQ_EP93XX_ETHERNET_PME 57 +#define IRQ_EP93XX_DSP 58 +#define IRQ_EP93XX_GPIO_AB 59 +#define IRQ_EP93XX_SAI 60 +#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff + +#define NR_EP93XX_IRQS 64 + +#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) +#define EP93XX_BOARD_IRQS 32 + +#define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS) + + +#endif diff --git a/include/asm-arm/arch-ep93xx/memory.h b/include/asm-arm/arch-ep93xx/memory.h new file mode 100644 index 000000000000..4b1a5c7c8363 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/memory.h @@ -0,0 +1,14 @@ +/* + * linux/include/asm-arm/arch-ep93xx/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +#define __bus_to_virt(x) __phys_to_virt(x) +#define __virt_to_bus(x) __virt_to_phys(x) + + +#endif diff --git a/include/asm-arm/arch-ep93xx/platform.h b/include/asm-arm/arch-ep93xx/platform.h new file mode 100644 index 000000000000..df9cbb6ef660 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/platform.h @@ -0,0 +1,14 @@ +/* + * linux/include/asm-arm/arch-ep93xx/platform.h + */ + +#ifndef __ASSEMBLY__ + +void ep93xx_map_io(void); +void ep93xx_init_irq(void); +void ep93xx_init_time(unsigned long); +void ep93xx_init_devices(void); +extern struct sys_timer ep93xx_timer; + + +#endif diff --git a/include/asm-arm/arch-ep93xx/system.h b/include/asm-arm/arch-ep93xx/system.h new file mode 100644 index 000000000000..79b718586746 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/system.h @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/arch-ep93xx/system.h + */ + +#include + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + u32 devicecfg; + + local_irq_disable(); + + devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG); + __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); + __raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG); + __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); + __raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG); + + while (1) + ; +} diff --git a/include/asm-arm/arch-ep93xx/timex.h b/include/asm-arm/arch-ep93xx/timex.h new file mode 100644 index 000000000000..4140bddc97e2 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/timex.h @@ -0,0 +1,5 @@ +/* + * linux/include/asm-arm/arch-ep93xx/timex.h + */ + +#define CLOCK_TICK_RATE 983040 diff --git a/include/asm-arm/arch-ep93xx/ts72xx.h b/include/asm-arm/arch-ep93xx/ts72xx.h new file mode 100644 index 000000000000..412215e77f44 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/ts72xx.h @@ -0,0 +1,90 @@ +/* + * linux/include/asm-arm/arch-ep93xx/ts72xx.h + */ + +/* + * TS72xx memory map: + * + * virt phys size + * febff000 22000000 4K model number register + * febfe000 22400000 4K options register + * febfd000 22800000 4K options register #2 + * febfc000 [67]0000000 4K NAND data register + * febfb000 [67]0400000 4K NAND control register + * febfa000 [67]0800000 4K NAND busy register + */ + +#define TS72XX_MODEL_PHYS_BASE 0x22000000 +#define TS72XX_MODEL_VIRT_BASE 0xfebff000 +#define TS72XX_MODEL_SIZE 0x00001000 + +#define TS72XX_MODEL_TS7200 0x00 +#define TS72XX_MODEL_TS7250 0x01 +#define TS72XX_MODEL_TS7260 0x02 + + +#define TS72XX_OPTIONS_PHYS_BASE 0x22400000 +#define TS72XX_OPTIONS_VIRT_BASE 0xfebfe000 +#define TS72XX_OPTIONS_SIZE 0x00001000 + +#define TS72XX_OPTIONS_COM2_RS485 0x02 +#define TS72XX_OPTIONS_MAX197 0x01 + + +#define TS72XX_OPTIONS2_PHYS_BASE 0x22800000 +#define TS72XX_OPTIONS2_VIRT_BASE 0xfebfd000 +#define TS72XX_OPTIONS2_SIZE 0x00001000 + +#define TS72XX_OPTIONS2_TS9420 0x04 +#define TS72XX_OPTIONS2_TS9420_BOOT 0x02 + + +#define TS72XX_NOR_PHYS_BASE 0x60000000 +#define TS72XX_NOR2_PHYS_BASE 0x62000000 + +#define TS72XX_NAND1_DATA_PHYS_BASE 0x60000000 +#define TS72XX_NAND2_DATA_PHYS_BASE 0x70000000 +#define TS72XX_NAND_DATA_VIRT_BASE 0xfebfc000 +#define TS72XX_NAND_DATA_SIZE 0x00001000 + +#define TS72XX_NAND1_CONTROL_PHYS_BASE 0x60400000 +#define TS72XX_NAND2_CONTROL_PHYS_BASE 0x70400000 +#define TS72XX_NAND_CONTROL_VIRT_BASE 0xfebfb000 +#define TS72XX_NAND_CONTROL_SIZE 0x00001000 + +#define TS72XX_NAND1_BUSY_PHYS_BASE 0x60800000 +#define TS72XX_NAND2_BUSY_PHYS_BASE 0x70800000 +#define TS72XX_NAND_BUSY_VIRT_BASE 0xfebfa000 +#define TS72XX_NAND_BUSY_SIZE 0x00001000 + + +#ifndef __ASSEMBLY__ +#include + +static inline int board_is_ts7200(void) +{ + return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200; +} + +static inline int board_is_ts7250(void) +{ + return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250; +} + +static inline int board_is_ts7260(void) +{ + return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260; +} + +static inline int is_max197_installed(void) +{ + return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) & + TS72XX_OPTIONS_MAX197); +} + +static inline int is_ts9420_installed(void) +{ + return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) & + TS72XX_OPTIONS2_TS9420); +} +#endif diff --git a/include/asm-arm/arch-ep93xx/uncompress.h b/include/asm-arm/arch-ep93xx/uncompress.h new file mode 100644 index 000000000000..4410d217077e --- /dev/null +++ b/include/asm-arm/arch-ep93xx/uncompress.h @@ -0,0 +1,53 @@ +/* + * linux/include/asm-arm/arch-ep93xx/uncompress.h + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include + +static unsigned char __raw_readb(unsigned int ptr) +{ + return *((volatile unsigned char *)ptr); +} + +static void __raw_writeb(unsigned char value, unsigned int ptr) +{ + *((volatile unsigned char *)ptr) = value; +} + + +#define PHYS_UART1_DATA 0x808c0000 +#define PHYS_UART1_FLAG 0x808c0018 +#define UART1_FLAG_TXFF 0x20 + +static __inline__ void putc(char c) +{ + int i; + + for (i = 0; i < 1000; i++) { + /* Transmit fifo not full? */ + if (!(__raw_readb(PHYS_UART1_FLAG) & UART1_FLAG_TXFF)) + break; + } + + __raw_writeb(c, PHYS_UART1_DATA); +} + +static void putstr(const char *s) +{ + while (*s) { + putc(*s); + if (*s == '\n') + putc('\r'); + s++; + } +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-ep93xx/vmalloc.h b/include/asm-arm/arch-ep93xx/vmalloc.h new file mode 100644 index 000000000000..205ea6b1cf5e --- /dev/null +++ b/include/asm-arm/arch-ep93xx/vmalloc.h @@ -0,0 +1,5 @@ +/* + * linux/include/asm-arm/arch-ep93xx/vmalloc.h + */ + +#define VMALLOC_END 0xfe800000 -- cgit v1.2.3-55-g7522 From a8e19667a42d752f3eca6eaa17aa5d6f93066dfe Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 20 Mar 2006 17:10:14 +0000 Subject: [ARM] 3371/1: ep93xx: gpio support Patch from Lennert Buytenhek Add support for setting the direction of and getting/setting the value of the 64 GPIO lines. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ep93xx/core.c | 68 +++++++++++++++++++ include/asm-arm/arch-ep93xx/ep93xx-regs.h | 1 + include/asm-arm/arch-ep93xx/gpio.h | 107 ++++++++++++++++++++++++++++++ 3 files changed, 176 insertions(+) create mode 100644 include/asm-arm/arch-ep93xx/gpio.h (limited to 'include') diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index f831f74dc8cc..7d3e79990fad 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -45,6 +45,7 @@ #include #include #include +#include #include @@ -146,6 +147,73 @@ struct sys_timer ep93xx_timer = { }; +/************************************************************************* + * GPIO handling for EP93xx + *************************************************************************/ +static unsigned char data_register_offset[8] = { + 0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40, +}; + +static unsigned char data_direction_register_offset[8] = { + 0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44, +}; + +void gpio_line_config(int line, int direction) +{ + unsigned int data_direction_register; + unsigned long flags; + unsigned char v; + + data_direction_register = + EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]); + + local_irq_save(flags); + if (direction == GPIO_OUT) { + v = __raw_readb(data_direction_register); + v |= 1 << (line & 7); + __raw_writeb(v, data_direction_register); + } else if (direction == GPIO_IN) { + v = __raw_readb(data_direction_register); + v &= ~(1 << (line & 7)); + __raw_writeb(v, data_direction_register); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_config); + +int gpio_line_get(int line) +{ + unsigned int data_register; + + data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]); + + return !!(__raw_readb(data_register) & (1 << (line & 7))); +} +EXPORT_SYMBOL(gpio_line_get); + +void gpio_line_set(int line, int value) +{ + unsigned int data_register; + unsigned long flags; + unsigned char v; + + data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]); + + local_irq_save(flags); + if (value == EP93XX_GPIO_HIGH) { + v = __raw_readb(data_register); + v |= 1 << (line & 7); + __raw_writeb(v, data_register); + } else if (value == EP93XX_GPIO_LOW) { + v = __raw_readb(data_register); + v &= ~(1 << (line & 7)); + __raw_writeb(v, data_register); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_set); + + /************************************************************************* * EP93xx IRQ handling *************************************************************************/ diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h index 693f23886e85..c1efacc83b75 100644 --- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h +++ b/include/asm-arm/arch-ep93xx/ep93xx-regs.h @@ -71,6 +71,7 @@ #define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) #define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) +#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) #define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h new file mode 100644 index 000000000000..1ee14a14cba0 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/gpio.h @@ -0,0 +1,107 @@ +/* + * linux/include/asm-arm/arch-ep93xx/gpio.h + */ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#define GPIO_IN 0 +#define GPIO_OUT 1 + +#define EP93XX_GPIO_LOW 0 +#define EP93XX_GPIO_HIGH 1 + +extern void gpio_line_config(int line, int direction); +extern int gpio_line_get(int line); +extern void gpio_line_set(int line, int value); + +/* GPIO port A. */ +#define EP93XX_GPIO_LINE_A(x) ((x) + 0) +#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) +#define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1) +#define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2) +#define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3) +#define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4) +#define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5) +#define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6) +#define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7) + +/* GPIO port B. */ +#define EP93XX_GPIO_LINE_B(x) ((x) + 8) +#define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0) +#define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1) +#define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2) +#define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3) +#define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4) +#define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5) +#define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6) +#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7) + +/* GPIO port C. */ +#define EP93XX_GPIO_LINE_C(x) ((x) + 16) +#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0) +#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1) +#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2) +#define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3) +#define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4) +#define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5) +#define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6) +#define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7) + +/* GPIO port D. */ +#define EP93XX_GPIO_LINE_D(x) ((x) + 24) +#define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0) +#define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1) +#define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2) +#define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3) +#define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4) +#define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5) +#define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6) +#define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7) + +/* GPIO port E. */ +#define EP93XX_GPIO_LINE_E(x) ((x) + 32) +#define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0) +#define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1) +#define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2) +#define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3) +#define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4) +#define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5) +#define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6) +#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7) + +/* GPIO port F. */ +#define EP93XX_GPIO_LINE_F(x) ((x) + 40) +#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0) +#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1) +#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2) +#define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3) +#define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4) +#define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5) +#define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6) +#define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7) + +/* GPIO port G. */ +#define EP93XX_GPIO_LINE_G(x) ((x) + 48) +#define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0) +#define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1) +#define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2) +#define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3) +#define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4) +#define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5) +#define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6) +#define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7) + +/* GPIO port H. */ +#define EP93XX_GPIO_LINE_H(x) ((x) + 56) +#define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0) +#define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1) +#define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2) +#define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3) +#define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4) +#define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5) +#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6) +#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7) + + +#endif -- cgit v1.2.3-55-g7522 From 18ec5c731271939acb414614e964c15c8ef52156 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 20 Mar 2006 17:10:17 +0000 Subject: [ARM] 3373/1: move uengine loader to arch/arm/common Patch from Lennert Buytenhek Move the uengine loader from arch/arm/mach-ixp2000 to arch/arm/common so that ixp23xx can use it too. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/common/Makefile | 1 + arch/arm/common/uengine.c | 473 +++++++++++++++++++++++++++++++++ arch/arm/mach-ixp2000/Makefile | 2 +- arch/arm/mach-ixp2000/uengine.c | 473 --------------------------------- drivers/net/ixp2000/enp2611.c | 2 +- drivers/net/ixp2000/ixpdev.c | 2 +- include/asm-arm/arch-ixp2000/uengine.h | 62 ----- include/asm-arm/hardware/uengine.h | 62 +++++ 8 files changed, 539 insertions(+), 538 deletions(-) create mode 100644 arch/arm/common/uengine.c delete mode 100644 arch/arm/mach-ixp2000/uengine.c delete mode 100644 include/asm-arm/arch-ixp2000/uengine.h create mode 100644 include/asm-arm/hardware/uengine.h (limited to 'include') diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index c81a2ff6b5be..847e3e6356c6 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_SHARP_LOCOMO) += locomo.o obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o obj-$(CONFIG_SHARPSL_PM) += sharpsl_pm.o obj-$(CONFIG_SHARP_SCOOP) += scoop.o +obj-$(CONFIG_ARCH_IXP2000) += uengine.o diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c new file mode 100644 index 000000000000..a1310b71004e --- /dev/null +++ b/arch/arm/common/uengine.c @@ -0,0 +1,473 @@ +/* + * Generic library functions for the microengines found on the Intel + * IXP2000 series of network processors. + * + * Copyright (C) 2004, 2005 Lennert Buytenhek + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2.1 of the + * License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USTORE_ADDRESS 0x000 +#define USTORE_DATA_LOWER 0x004 +#define USTORE_DATA_UPPER 0x008 +#define CTX_ENABLES 0x018 +#define CC_ENABLE 0x01c +#define CSR_CTX_POINTER 0x020 +#define INDIRECT_CTX_STS 0x040 +#define ACTIVE_CTX_STS 0x044 +#define INDIRECT_CTX_SIG_EVENTS 0x048 +#define INDIRECT_CTX_WAKEUP_EVENTS 0x050 +#define NN_PUT 0x080 +#define NN_GET 0x084 +#define TIMESTAMP_LOW 0x0c0 +#define TIMESTAMP_HIGH 0x0c4 +#define T_INDEX_BYTE_INDEX 0x0f4 +#define LOCAL_CSR_STATUS 0x180 + +u32 ixp2000_uengine_mask; + +static void *ixp2000_uengine_csr_area(int uengine) +{ + return ((void *)IXP2000_UENGINE_CSR_VIRT_BASE) + (uengine << 10); +} + +/* + * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR + * space means that the microengine we tried to access was also trying + * to access its own CSR space on the same clock cycle as we did. When + * this happens, we lose the arbitration process by default, and the + * read or write we tried to do was not actually performed, so we try + * again until it succeeds. + */ +u32 ixp2000_uengine_csr_read(int uengine, int offset) +{ + void *uebase; + u32 *local_csr_status; + u32 *reg; + u32 value; + + uebase = ixp2000_uengine_csr_area(uengine); + + local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS); + reg = (u32 *)(uebase + offset); + do { + value = ixp2000_reg_read(reg); + } while (ixp2000_reg_read(local_csr_status) & 1); + + return value; +} +EXPORT_SYMBOL(ixp2000_uengine_csr_read); + +void ixp2000_uengine_csr_write(int uengine, int offset, u32 value) +{ + void *uebase; + u32 *local_csr_status; + u32 *reg; + + uebase = ixp2000_uengine_csr_area(uengine); + + local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS); + reg = (u32 *)(uebase + offset); + do { + ixp2000_reg_write(reg, value); + } while (ixp2000_reg_read(local_csr_status) & 1); +} +EXPORT_SYMBOL(ixp2000_uengine_csr_write); + +void ixp2000_uengine_reset(u32 uengine_mask) +{ + ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask); + ixp2000_reg_wrb(IXP2000_RESET1, 0); +} +EXPORT_SYMBOL(ixp2000_uengine_reset); + +void ixp2000_uengine_set_mode(int uengine, u32 mode) +{ + /* + * CTL_STR_PAR_EN: unconditionally enable parity checking on + * control store. + */ + mode |= 0x10000000; + ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode); + + /* + * Enable updating of condition codes. + */ + ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000); + + /* + * Initialise other per-microengine registers. + */ + ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00); + ixp2000_uengine_csr_write(uengine, NN_GET, 0x00); + ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0); +} +EXPORT_SYMBOL(ixp2000_uengine_set_mode); + +static int make_even_parity(u32 x) +{ + return hweight32(x) & 1; +} + +static void ustore_write(int uengine, u64 insn) +{ + /* + * Generate even parity for top and bottom 20 bits. + */ + insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41; + insn |= (u64)make_even_parity(insn & 0x000fffff) << 40; + + /* + * Write to microstore. The second write auto-increments + * the USTORE_ADDRESS index register. + */ + ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn); + ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32)); +} + +void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns) +{ + int i; + + /* + * Start writing to microstore at address 0. + */ + ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000); + for (i = 0; i < insns; i++) { + u64 insn; + + insn = (((u64)ucode[0]) << 32) | + (((u64)ucode[1]) << 24) | + (((u64)ucode[2]) << 16) | + (((u64)ucode[3]) << 8) | + ((u64)ucode[4]); + ucode += 5; + + ustore_write(uengine, insn); + } + + /* + * Pad with a few NOPs at the end (to avoid the microengine + * aborting as it prefetches beyond the last instruction), unless + * we run off the end of the instruction store first, at which + * point the address register will wrap back to zero. + */ + for (i = 0; i < 4; i++) { + u32 addr; + + addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS); + if (addr == 0x80000000) + break; + ustore_write(uengine, 0xf0000c0300ULL); + } + + /* + * End programming. + */ + ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000); +} +EXPORT_SYMBOL(ixp2000_uengine_load_microcode); + +void ixp2000_uengine_init_context(int uengine, int context, int pc) +{ + /* + * Select the right context for indirect access. + */ + ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context); + + /* + * Initialise signal masks to immediately go to Ready state. + */ + ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1); + ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1); + + /* + * Set program counter. + */ + ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc); +} +EXPORT_SYMBOL(ixp2000_uengine_init_context); + +void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask) +{ + u32 mask; + + /* + * Enable the specified context to go to Executing state. + */ + mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES); + mask |= ctx_mask << 8; + ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask); +} +EXPORT_SYMBOL(ixp2000_uengine_start_contexts); + +void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask) +{ + u32 mask; + + /* + * Disable the Ready->Executing transition. Note that this + * does not stop the context until it voluntarily yields. + */ + mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES); + mask &= ~(ctx_mask << 8); + ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask); +} +EXPORT_SYMBOL(ixp2000_uengine_stop_contexts); + +static int check_ixp_type(struct ixp2000_uengine_code *c) +{ + u32 product_id; + u32 rev; + + product_id = ixp2000_reg_read(IXP2000_PRODUCT_ID); + if (((product_id >> 16) & 0x1f) != 0) + return 0; + + switch ((product_id >> 8) & 0xff) { + case 0: /* IXP2800 */ + if (!(c->cpu_model_bitmask & 4)) + return 0; + break; + + case 1: /* IXP2850 */ + if (!(c->cpu_model_bitmask & 8)) + return 0; + break; + + case 2: /* IXP2400 */ + if (!(c->cpu_model_bitmask & 2)) + return 0; + break; + + default: + return 0; + } + + rev = product_id & 0xff; + if (rev < c->cpu_min_revision || rev > c->cpu_max_revision) + return 0; + + return 1; +} + +static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) +{ + int offset; + int i; + + offset = 0; + + for (i = 0; i < 128; i++) { + u8 b3; + u8 b2; + u8 b1; + u8 b0; + + b3 = (gpr_a[i] >> 24) & 0xff; + b2 = (gpr_a[i] >> 16) & 0xff; + b1 = (gpr_a[i] >> 8) & 0xff; + b0 = gpr_a[i] & 0xff; + + // immed[@ai, (b1 << 8) | b0] + // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII + ucode[offset++] = 0xf0; + ucode[offset++] = (b1 >> 4); + ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6); + ucode[offset++] = (b0 << 2); + ucode[offset++] = 0x80 | i; + + // immed_w1[@ai, (b3 << 8) | b2] + // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII + ucode[offset++] = 0xf4; + ucode[offset++] = 0x40 | (b3 >> 4); + ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6); + ucode[offset++] = (b2 << 2); + ucode[offset++] = 0x80 | i; + } + + for (i = 0; i < 128; i++) { + u8 b3; + u8 b2; + u8 b1; + u8 b0; + + b3 = (gpr_b[i] >> 24) & 0xff; + b2 = (gpr_b[i] >> 16) & 0xff; + b1 = (gpr_b[i] >> 8) & 0xff; + b0 = gpr_b[i] & 0xff; + + // immed[@bi, (b1 << 8) | b0] + // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV + ucode[offset++] = 0xf0; + ucode[offset++] = (b1 >> 4); + ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6); + ucode[offset++] = (i << 2) | 0x03; + ucode[offset++] = b0; + + // immed_w1[@bi, (b3 << 8) | b2] + // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV + ucode[offset++] = 0xf4; + ucode[offset++] = 0x40 | (b3 >> 4); + ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6); + ucode[offset++] = (i << 2) | 0x03; + ucode[offset++] = b2; + } + + // ctx_arb[kill] + ucode[offset++] = 0xe0; + ucode[offset++] = 0x00; + ucode[offset++] = 0x01; + ucode[offset++] = 0x00; + ucode[offset++] = 0x00; +} + +static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c) +{ + int per_ctx_regs; + u32 *gpr_a; + u32 *gpr_b; + u8 *ucode; + int i; + + gpr_a = kmalloc(128 * sizeof(u32), GFP_KERNEL); + gpr_b = kmalloc(128 * sizeof(u32), GFP_KERNEL); + ucode = kmalloc(513 * 5, GFP_KERNEL); + if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) { + kfree(ucode); + kfree(gpr_b); + kfree(gpr_a); + return 1; + } + + per_ctx_regs = 16; + if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS) + per_ctx_regs = 32; + + memset(gpr_a, 0, sizeof(gpr_a)); + memset(gpr_b, 0, sizeof(gpr_b)); + for (i = 0; i < 256; i++) { + struct ixp2000_reg_value *r = c->initial_reg_values + i; + u32 *bank; + int inc; + int j; + + if (r->reg == -1) + break; + + bank = (r->reg & 0x400) ? gpr_b : gpr_a; + inc = (r->reg & 0x80) ? 128 : per_ctx_regs; + + j = r->reg & 0x7f; + while (j < 128) { + bank[j] = r->value; + j += inc; + } + } + + generate_ucode(ucode, gpr_a, gpr_b); + ixp2000_uengine_load_microcode(uengine, ucode, 513); + ixp2000_uengine_init_context(uengine, 0, 0); + ixp2000_uengine_start_contexts(uengine, 0x01); + for (i = 0; i < 100; i++) { + u32 status; + + status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS); + if (!(status & 0x80000000)) + break; + } + ixp2000_uengine_stop_contexts(uengine, 0x01); + + kfree(ucode); + kfree(gpr_b); + kfree(gpr_a); + + return !!(i == 100); +} + +int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c) +{ + int ctx; + + if (!check_ixp_type(c)) + return 1; + + if (!(ixp2000_uengine_mask & (1 << uengine))) + return 1; + + ixp2000_uengine_reset(1 << uengine); + ixp2000_uengine_set_mode(uengine, c->uengine_parameters); + if (set_initial_registers(uengine, c)) + return 1; + ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns); + + for (ctx = 0; ctx < 8; ctx++) + ixp2000_uengine_init_context(uengine, ctx, 0); + + return 0; +} +EXPORT_SYMBOL(ixp2000_uengine_load); + + +static int __init ixp2000_uengine_init(void) +{ + int uengine; + u32 value; + + /* + * Determine number of microengines present. + */ + switch ((ixp2000_reg_read(IXP2000_PRODUCT_ID) >> 8) & 0x1fff) { + case 0: /* IXP2800 */ + case 1: /* IXP2850 */ + ixp2000_uengine_mask = 0x00ff00ff; + break; + + case 2: /* IXP2400 */ + ixp2000_uengine_mask = 0x000f000f; + break; + + default: + printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n", + (unsigned int)ixp2000_reg_read(IXP2000_PRODUCT_ID)); + ixp2000_uengine_mask = 0x00000000; + break; + } + + /* + * Reset microengines. + */ + ixp2000_uengine_reset(ixp2000_uengine_mask); + + /* + * Synchronise timestamp counters across all microengines. + */ + value = ixp2000_reg_read(IXP2000_MISC_CONTROL); + ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80); + for (uengine = 0; uengine < 32; uengine++) { + if (ixp2000_uengine_mask & (1 << uengine)) { + ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0); + ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0); + } + } + ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80); + + return 0; +} + +subsys_initcall(ixp2000_uengine_init); diff --git a/arch/arm/mach-ixp2000/Makefile b/arch/arm/mach-ixp2000/Makefile index 9621aeb61f46..1e6139d42a92 100644 --- a/arch/arm/mach-ixp2000/Makefile +++ b/arch/arm/mach-ixp2000/Makefile @@ -1,7 +1,7 @@ # # Makefile for the linux kernel. # -obj-y := core.o pci.o uengine.o +obj-y := core.o pci.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-ixp2000/uengine.c b/arch/arm/mach-ixp2000/uengine.c deleted file mode 100644 index ec4e007a22ef..000000000000 --- a/arch/arm/mach-ixp2000/uengine.c +++ /dev/null @@ -1,473 +0,0 @@ -/* - * Generic library functions for the microengines found on the Intel - * IXP2000 series of network processors. - * - * Copyright (C) 2004, 2005 Lennert Buytenhek - * Dedicated to Marija Kulikova. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2.1 of the - * License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define USTORE_ADDRESS 0x000 -#define USTORE_DATA_LOWER 0x004 -#define USTORE_DATA_UPPER 0x008 -#define CTX_ENABLES 0x018 -#define CC_ENABLE 0x01c -#define CSR_CTX_POINTER 0x020 -#define INDIRECT_CTX_STS 0x040 -#define ACTIVE_CTX_STS 0x044 -#define INDIRECT_CTX_SIG_EVENTS 0x048 -#define INDIRECT_CTX_WAKEUP_EVENTS 0x050 -#define NN_PUT 0x080 -#define NN_GET 0x084 -#define TIMESTAMP_LOW 0x0c0 -#define TIMESTAMP_HIGH 0x0c4 -#define T_INDEX_BYTE_INDEX 0x0f4 -#define LOCAL_CSR_STATUS 0x180 - -u32 ixp2000_uengine_mask; - -static void *ixp2000_uengine_csr_area(int uengine) -{ - return ((void *)IXP2000_UENGINE_CSR_VIRT_BASE) + (uengine << 10); -} - -/* - * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR - * space means that the microengine we tried to access was also trying - * to access its own CSR space on the same clock cycle as we did. When - * this happens, we lose the arbitration process by default, and the - * read or write we tried to do was not actually performed, so we try - * again until it succeeds. - */ -u32 ixp2000_uengine_csr_read(int uengine, int offset) -{ - void *uebase; - u32 *local_csr_status; - u32 *reg; - u32 value; - - uebase = ixp2000_uengine_csr_area(uengine); - - local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS); - reg = (u32 *)(uebase + offset); - do { - value = ixp2000_reg_read(reg); - } while (ixp2000_reg_read(local_csr_status) & 1); - - return value; -} -EXPORT_SYMBOL(ixp2000_uengine_csr_read); - -void ixp2000_uengine_csr_write(int uengine, int offset, u32 value) -{ - void *uebase; - u32 *local_csr_status; - u32 *reg; - - uebase = ixp2000_uengine_csr_area(uengine); - - local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS); - reg = (u32 *)(uebase + offset); - do { - ixp2000_reg_write(reg, value); - } while (ixp2000_reg_read(local_csr_status) & 1); -} -EXPORT_SYMBOL(ixp2000_uengine_csr_write); - -void ixp2000_uengine_reset(u32 uengine_mask) -{ - ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask); - ixp2000_reg_wrb(IXP2000_RESET1, 0); -} -EXPORT_SYMBOL(ixp2000_uengine_reset); - -void ixp2000_uengine_set_mode(int uengine, u32 mode) -{ - /* - * CTL_STR_PAR_EN: unconditionally enable parity checking on - * control store. - */ - mode |= 0x10000000; - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode); - - /* - * Enable updating of condition codes. - */ - ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000); - - /* - * Initialise other per-microengine registers. - */ - ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00); - ixp2000_uengine_csr_write(uengine, NN_GET, 0x00); - ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0); -} -EXPORT_SYMBOL(ixp2000_uengine_set_mode); - -static int make_even_parity(u32 x) -{ - return hweight32(x) & 1; -} - -static void ustore_write(int uengine, u64 insn) -{ - /* - * Generate even parity for top and bottom 20 bits. - */ - insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41; - insn |= (u64)make_even_parity(insn & 0x000fffff) << 40; - - /* - * Write to microstore. The second write auto-increments - * the USTORE_ADDRESS index register. - */ - ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn); - ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32)); -} - -void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns) -{ - int i; - - /* - * Start writing to microstore at address 0. - */ - ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000); - for (i = 0; i < insns; i++) { - u64 insn; - - insn = (((u64)ucode[0]) << 32) | - (((u64)ucode[1]) << 24) | - (((u64)ucode[2]) << 16) | - (((u64)ucode[3]) << 8) | - ((u64)ucode[4]); - ucode += 5; - - ustore_write(uengine, insn); - } - - /* - * Pad with a few NOPs at the end (to avoid the microengine - * aborting as it prefetches beyond the last instruction), unless - * we run off the end of the instruction store first, at which - * point the address register will wrap back to zero. - */ - for (i = 0; i < 4; i++) { - u32 addr; - - addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS); - if (addr == 0x80000000) - break; - ustore_write(uengine, 0xf0000c0300ULL); - } - - /* - * End programming. - */ - ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000); -} -EXPORT_SYMBOL(ixp2000_uengine_load_microcode); - -void ixp2000_uengine_init_context(int uengine, int context, int pc) -{ - /* - * Select the right context for indirect access. - */ - ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context); - - /* - * Initialise signal masks to immediately go to Ready state. - */ - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1); - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1); - - /* - * Set program counter. - */ - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc); -} -EXPORT_SYMBOL(ixp2000_uengine_init_context); - -void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask) -{ - u32 mask; - - /* - * Enable the specified context to go to Executing state. - */ - mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES); - mask |= ctx_mask << 8; - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask); -} -EXPORT_SYMBOL(ixp2000_uengine_start_contexts); - -void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask) -{ - u32 mask; - - /* - * Disable the Ready->Executing transition. Note that this - * does not stop the context until it voluntarily yields. - */ - mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES); - mask &= ~(ctx_mask << 8); - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask); -} -EXPORT_SYMBOL(ixp2000_uengine_stop_contexts); - -static int check_ixp_type(struct ixp2000_uengine_code *c) -{ - u32 product_id; - u32 rev; - - product_id = ixp2000_reg_read(IXP2000_PRODUCT_ID); - if (((product_id >> 16) & 0x1f) != 0) - return 0; - - switch ((product_id >> 8) & 0xff) { - case 0: /* IXP2800 */ - if (!(c->cpu_model_bitmask & 4)) - return 0; - break; - - case 1: /* IXP2850 */ - if (!(c->cpu_model_bitmask & 8)) - return 0; - break; - - case 2: /* IXP2400 */ - if (!(c->cpu_model_bitmask & 2)) - return 0; - break; - - default: - return 0; - } - - rev = product_id & 0xff; - if (rev < c->cpu_min_revision || rev > c->cpu_max_revision) - return 0; - - return 1; -} - -static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) -{ - int offset; - int i; - - offset = 0; - - for (i = 0; i < 128; i++) { - u8 b3; - u8 b2; - u8 b1; - u8 b0; - - b3 = (gpr_a[i] >> 24) & 0xff; - b2 = (gpr_a[i] >> 16) & 0xff; - b1 = (gpr_a[i] >> 8) & 0xff; - b0 = gpr_a[i] & 0xff; - - // immed[@ai, (b1 << 8) | b0] - // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII - ucode[offset++] = 0xf0; - ucode[offset++] = (b1 >> 4); - ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6); - ucode[offset++] = (b0 << 2); - ucode[offset++] = 0x80 | i; - - // immed_w1[@ai, (b3 << 8) | b2] - // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII - ucode[offset++] = 0xf4; - ucode[offset++] = 0x40 | (b3 >> 4); - ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6); - ucode[offset++] = (b2 << 2); - ucode[offset++] = 0x80 | i; - } - - for (i = 0; i < 128; i++) { - u8 b3; - u8 b2; - u8 b1; - u8 b0; - - b3 = (gpr_b[i] >> 24) & 0xff; - b2 = (gpr_b[i] >> 16) & 0xff; - b1 = (gpr_b[i] >> 8) & 0xff; - b0 = gpr_b[i] & 0xff; - - // immed[@bi, (b1 << 8) | b0] - // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV - ucode[offset++] = 0xf0; - ucode[offset++] = (b1 >> 4); - ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6); - ucode[offset++] = (i << 2) | 0x03; - ucode[offset++] = b0; - - // immed_w1[@bi, (b3 << 8) | b2] - // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV - ucode[offset++] = 0xf4; - ucode[offset++] = 0x40 | (b3 >> 4); - ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6); - ucode[offset++] = (i << 2) | 0x03; - ucode[offset++] = b2; - } - - // ctx_arb[kill] - ucode[offset++] = 0xe0; - ucode[offset++] = 0x00; - ucode[offset++] = 0x01; - ucode[offset++] = 0x00; - ucode[offset++] = 0x00; -} - -static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c) -{ - int per_ctx_regs; - u32 *gpr_a; - u32 *gpr_b; - u8 *ucode; - int i; - - gpr_a = kmalloc(128 * sizeof(u32), GFP_KERNEL); - gpr_b = kmalloc(128 * sizeof(u32), GFP_KERNEL); - ucode = kmalloc(513 * 5, GFP_KERNEL); - if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) { - kfree(ucode); - kfree(gpr_b); - kfree(gpr_a); - return 1; - } - - per_ctx_regs = 16; - if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS) - per_ctx_regs = 32; - - memset(gpr_a, 0, sizeof(gpr_a)); - memset(gpr_b, 0, sizeof(gpr_b)); - for (i = 0; i < 256; i++) { - struct ixp2000_reg_value *r = c->initial_reg_values + i; - u32 *bank; - int inc; - int j; - - if (r->reg == -1) - break; - - bank = (r->reg & 0x400) ? gpr_b : gpr_a; - inc = (r->reg & 0x80) ? 128 : per_ctx_regs; - - j = r->reg & 0x7f; - while (j < 128) { - bank[j] = r->value; - j += inc; - } - } - - generate_ucode(ucode, gpr_a, gpr_b); - ixp2000_uengine_load_microcode(uengine, ucode, 513); - ixp2000_uengine_init_context(uengine, 0, 0); - ixp2000_uengine_start_contexts(uengine, 0x01); - for (i = 0; i < 100; i++) { - u32 status; - - status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS); - if (!(status & 0x80000000)) - break; - } - ixp2000_uengine_stop_contexts(uengine, 0x01); - - kfree(ucode); - kfree(gpr_b); - kfree(gpr_a); - - return !!(i == 100); -} - -int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c) -{ - int ctx; - - if (!check_ixp_type(c)) - return 1; - - if (!(ixp2000_uengine_mask & (1 << uengine))) - return 1; - - ixp2000_uengine_reset(1 << uengine); - ixp2000_uengine_set_mode(uengine, c->uengine_parameters); - if (set_initial_registers(uengine, c)) - return 1; - ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns); - - for (ctx = 0; ctx < 8; ctx++) - ixp2000_uengine_init_context(uengine, ctx, 0); - - return 0; -} -EXPORT_SYMBOL(ixp2000_uengine_load); - - -static int __init ixp2000_uengine_init(void) -{ - int uengine; - u32 value; - - /* - * Determine number of microengines present. - */ - switch ((ixp2000_reg_read(IXP2000_PRODUCT_ID) >> 8) & 0x1fff) { - case 0: /* IXP2800 */ - case 1: /* IXP2850 */ - ixp2000_uengine_mask = 0x00ff00ff; - break; - - case 2: /* IXP2400 */ - ixp2000_uengine_mask = 0x000f000f; - break; - - default: - printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n", - (unsigned int)ixp2000_reg_read(IXP2000_PRODUCT_ID)); - ixp2000_uengine_mask = 0x00000000; - break; - } - - /* - * Reset microengines. - */ - ixp2000_uengine_reset(ixp2000_uengine_mask); - - /* - * Synchronise timestamp counters across all microengines. - */ - value = ixp2000_reg_read(IXP2000_MISC_CONTROL); - ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80); - for (uengine = 0; uengine < 32; uengine++) { - if (ixp2000_uengine_mask & (1 << uengine)) { - ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0); - ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0); - } - } - ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80); - - return 0; -} - -subsys_initcall(ixp2000_uengine_init); diff --git a/drivers/net/ixp2000/enp2611.c b/drivers/net/ixp2000/enp2611.c index d82651a97bae..6f7dce8eba51 100644 --- a/drivers/net/ixp2000/enp2611.c +++ b/drivers/net/ixp2000/enp2611.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include "ixpdev.h" diff --git a/drivers/net/ixp2000/ixpdev.c b/drivers/net/ixp2000/ixpdev.c index 09f03f493bea..77f104a005f3 100644 --- a/drivers/net/ixp2000/ixpdev.c +++ b/drivers/net/ixp2000/ixpdev.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include "ixp2400_rx.ucode" diff --git a/include/asm-arm/arch-ixp2000/uengine.h b/include/asm-arm/arch-ixp2000/uengine.h deleted file mode 100644 index b442d65c6593..000000000000 --- a/include/asm-arm/arch-ixp2000/uengine.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Generic library functions for the microengines found on the Intel - * IXP2000 series of network processors. - * - * Copyright (C) 2004, 2005 Lennert Buytenhek - * Dedicated to Marija Kulikova. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2.1 of the - * License, or (at your option) any later version. - */ - -#ifndef __IXP2000_UENGINE_H -#define __IXP2000_UENGINE_H - -extern u32 ixp2000_uengine_mask; - -struct ixp2000_uengine_code -{ - u32 cpu_model_bitmask; - u8 cpu_min_revision; - u8 cpu_max_revision; - - u32 uengine_parameters; - - struct ixp2000_reg_value { - int reg; - u32 value; - } *initial_reg_values; - - int num_insns; - u8 *insns; -}; - -u32 ixp2000_uengine_csr_read(int uengine, int offset); -void ixp2000_uengine_csr_write(int uengine, int offset, u32 value); -void ixp2000_uengine_reset(u32 uengine_mask); -void ixp2000_uengine_set_mode(int uengine, u32 mode); -void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns); -void ixp2000_uengine_init_context(int uengine, int context, int pc); -void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask); -void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask); -int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c); - -#define IXP2000_UENGINE_8_CONTEXTS 0x00000000 -#define IXP2000_UENGINE_4_CONTEXTS 0x80000000 -#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000 -#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000 -#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000 -#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000 -#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000 -#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000 -#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000 -#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000 - - -#endif diff --git a/include/asm-arm/hardware/uengine.h b/include/asm-arm/hardware/uengine.h new file mode 100644 index 000000000000..b442d65c6593 --- /dev/null +++ b/include/asm-arm/hardware/uengine.h @@ -0,0 +1,62 @@ +/* + * Generic library functions for the microengines found on the Intel + * IXP2000 series of network processors. + * + * Copyright (C) 2004, 2005 Lennert Buytenhek + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2.1 of the + * License, or (at your option) any later version. + */ + +#ifndef __IXP2000_UENGINE_H +#define __IXP2000_UENGINE_H + +extern u32 ixp2000_uengine_mask; + +struct ixp2000_uengine_code +{ + u32 cpu_model_bitmask; + u8 cpu_min_revision; + u8 cpu_max_revision; + + u32 uengine_parameters; + + struct ixp2000_reg_value { + int reg; + u32 value; + } *initial_reg_values; + + int num_insns; + u8 *insns; +}; + +u32 ixp2000_uengine_csr_read(int uengine, int offset); +void ixp2000_uengine_csr_write(int uengine, int offset, u32 value); +void ixp2000_uengine_reset(u32 uengine_mask); +void ixp2000_uengine_set_mode(int uengine, u32 mode); +void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns); +void ixp2000_uengine_init_context(int uengine, int context, int pc); +void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask); +void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask); +int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c); + +#define IXP2000_UENGINE_8_CONTEXTS 0x00000000 +#define IXP2000_UENGINE_4_CONTEXTS 0x80000000 +#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000 +#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000 +#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000 +#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000 +#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000 +#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000 +#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000 +#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000 +#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000 +#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000 +#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000 +#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000 + + +#endif -- cgit v1.2.3-55-g7522 From bd20ff5793b4ece4fa3e9e0fcf8e6bbd93526215 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 20 Mar 2006 21:02:37 +0000 Subject: [ARM] 3374/1: ep93xx: gpio interrupt support Patch from Lennert Buytenhek Add GPIO interrupt support for the first 16 GPIO lines (port A and B.) Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ep93xx/core.c | 133 ++++++++++++++++++++++++++++++ include/asm-arm/arch-ep93xx/ep93xx-regs.h | 10 +++ include/asm-arm/arch-ep93xx/irqs.h | 4 +- 3 files changed, 146 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 7d3e79990fad..865427bfad7e 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -150,6 +150,26 @@ struct sys_timer ep93xx_timer = { /************************************************************************* * GPIO handling for EP93xx *************************************************************************/ +static unsigned char gpio_int_enable[2]; +static unsigned char gpio_int_type1[2]; +static unsigned char gpio_int_type2[2]; + +static void update_gpio_ab_int_params(int port) +{ + if (port == 0) { + __raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE); + __raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2); + __raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1); + __raw_writeb(gpio_int_enable[0], EP93XX_GPIO_A_INT_ENABLE); + } else if (port == 1) { + __raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE); + __raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2); + __raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1); + __raw_writeb(gpio_int_enable[1], EP93XX_GPIO_B_INT_ENABLE); + } +} + + static unsigned char data_register_offset[8] = { 0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40, }; @@ -169,6 +189,11 @@ void gpio_line_config(int line, int direction) local_irq_save(flags); if (direction == GPIO_OUT) { + if (line >= 0 && line < 16) { + gpio_int_enable[line >> 3] &= ~(1 << (line & 7)); + update_gpio_ab_int_params(line >> 3); + } + v = __raw_readb(data_direction_register); v |= 1 << (line & 7); __raw_writeb(v, data_direction_register); @@ -217,10 +242,118 @@ EXPORT_SYMBOL(gpio_line_set); /************************************************************************* * EP93xx IRQ handling *************************************************************************/ +static void ep93xx_gpio_ab_irq_handler(unsigned int irq, + struct irqdesc *desc, struct pt_regs *regs) +{ + unsigned char status; + int i; + + status = __raw_readb(EP93XX_GPIO_A_INT_STATUS); + for (i = 0; i < 8; i++) { + if (status & (1 << i)) { + desc = irq_desc + IRQ_EP93XX_GPIO(0) + i; + desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc, regs); + } + } + + status = __raw_readb(EP93XX_GPIO_B_INT_STATUS); + for (i = 0; i < 8; i++) { + if (status & (1 << i)) { + desc = irq_desc + IRQ_EP93XX_GPIO(8) + i; + desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc, regs); + } + } +} + +static void ep93xx_gpio_ab_irq_mask_ack(unsigned int irq) +{ + int line = irq - IRQ_EP93XX_GPIO(0); + int port = line >> 3; + + gpio_int_enable[port] &= ~(1 << (line & 7)); + update_gpio_ab_int_params(port); + + if (line >> 3) { + __raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK); + } else { + __raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK); + } +} + +static void ep93xx_gpio_ab_irq_mask(unsigned int irq) +{ + int line = irq - IRQ_EP93XX_GPIO(0); + int port = line >> 3; + + gpio_int_enable[port] &= ~(1 << (line & 7)); + update_gpio_ab_int_params(port); +} + +static void ep93xx_gpio_ab_irq_unmask(unsigned int irq) +{ + int line = irq - IRQ_EP93XX_GPIO(0); + int port = line >> 3; + + gpio_int_enable[port] |= 1 << (line & 7); + update_gpio_ab_int_params(port); +} + + +/* + * gpio_int_type1 controls whether the interrupt is level (0) or + * edge (1) triggered, while gpio_int_type2 controls whether it + * triggers on low/falling (0) or high/rising (1). + */ +static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type) +{ + int port; + int line; + + line = irq - IRQ_EP93XX_GPIO(0); + gpio_line_config(line, GPIO_IN); + + port = line >> 3; + line &= 7; + + if (type & IRQT_RISING) { + gpio_int_type1[port] |= 1 << line; + gpio_int_type2[port] |= 1 << line; + } else if (type & IRQT_FALLING) { + gpio_int_type1[port] |= 1 << line; + gpio_int_type2[port] &= ~(1 << line); + } else if (type & IRQT_HIGH) { + gpio_int_type1[port] &= ~(1 << line); + gpio_int_type2[port] |= 1 << line; + } else if (type & IRQT_LOW) { + gpio_int_type1[port] &= ~(1 << line); + gpio_int_type2[port] &= ~(1 << line); + } + update_gpio_ab_int_params(port); + + return 0; +} + +static struct irqchip ep93xx_gpio_ab_irq_chip = { + .ack = ep93xx_gpio_ab_irq_mask_ack, + .mask = ep93xx_gpio_ab_irq_mask, + .unmask = ep93xx_gpio_ab_irq_unmask, + .set_type = ep93xx_gpio_ab_irq_type, +}; + + void __init ep93xx_init_irq(void) { + int irq; + vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK); vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK); + + for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) { + set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip); + set_irq_handler(irq, do_level_IRQ); + set_irq_flags(irq, IRQF_VALID); + } + set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); } diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h index c1efacc83b75..71cea0b5841b 100644 --- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h +++ b/include/asm-arm/arch-ep93xx/ep93xx-regs.h @@ -72,6 +72,16 @@ #define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) +#define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90) +#define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94) +#define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98) +#define EP93XX_GPIO_A_INT_ENABLE EP93XX_GPIO_REG(0x9c) +#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) +#define EP93XX_GPIO_B_INT_TYPE1 EP93XX_GPIO_REG(0xac) +#define EP93XX_GPIO_B_INT_TYPE2 EP93XX_GPIO_REG(0xb0) +#define EP93XX_GPIO_B_INT_ACK EP93XX_GPIO_REG(0xb4) +#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) +#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) #define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h index 8c10fb964faf..9a42f5de9e57 100644 --- a/include/asm-arm/arch-ep93xx/irqs.h +++ b/include/asm-arm/arch-ep93xx/irqs.h @@ -67,7 +67,9 @@ #define IRQ_EP93XX_SAI 60 #define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff -#define NR_EP93XX_IRQS 64 +#define IRQ_EP93XX_GPIO(x) (64 + (x)) + +#define NR_EP93XX_IRQS IRQ_EP93XX_GPIO(16) #define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) #define EP93XX_BOARD_IRQS 32 -- cgit v1.2.3-55-g7522 From bec1b8193651ea4394cc4d6e18152cb83e735f93 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 22 Mar 2006 10:22:58 +0000 Subject: [ARM] Quieten spurious IRQ detection Only issue a "nobody cared" warning after 99900 spurious interrupts. This avoids the occasional spurious interrupt causing warnings, as per x86. Signed-off-by: Russell King --- arch/arm/kernel/irq.c | 11 ++++++++--- include/asm-arm/mach/irq.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 1d50d2b98f55..2d5896b36181 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -305,14 +305,19 @@ report_bad_irq(unsigned int irq, struct pt_regs *regs, struct irqdesc *desc, int static int count = 100; struct irqaction *action; - if (!count || noirqdebug) + if (noirqdebug) return; - count--; - if (ret != IRQ_HANDLED && ret != IRQ_NONE) { + if (!count) + return; + count--; printk("irq%u: bogus retval mask %x\n", irq, ret); } else { + desc->irqs_unhandled++; + if (desc->irqs_unhandled <= 99900) + return; + desc->irqs_unhandled = 0; printk("irq%u: nobody cared\n", irq); } show_regs(regs); diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h index 76d05244c632..d4d420ecf3a8 100644 --- a/include/asm-arm/mach/irq.h +++ b/include/asm-arm/mach/irq.h @@ -74,6 +74,7 @@ struct irqdesc { unsigned int noautoenable : 1; /* don't automatically enable IRQ */ unsigned int unused :25; + unsigned int irqs_unhandled; struct proc_dir_entry *procdir; #ifdef CONFIG_SMP -- cgit v1.2.3-55-g7522 From e99053e07514e514611167ad648c65c87982c4d9 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 22 Mar 2006 20:14:09 +0000 Subject: [ARM] 3379/1: ixp2000: use generic 8250 debug macros Patch from Lennert Buytenhek The xscale UART in the ixp2000 is basically just an 8250 UART (with some extra bits and pieces), so we can use the generic 8250 debug macros on the ixp2000. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/arch-ixp2000/debug-macro.S | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-ixp2000/debug-macro.S b/include/asm-arm/arch-ixp2000/debug-macro.S index 5631e0889861..bc8b39654793 100644 --- a/include/asm-arm/arch-ixp2000/debug-macro.S +++ b/include/asm-arm/arch-ixp2000/debug-macro.S @@ -23,18 +23,5 @@ #endif .endm - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro busyuart,rd,rx -1002: ldrb \rd, [\rx, #0x14] - tst \rd, #0x20 - beq 1002b - .endm - - .macro waituart,rd,rx - nop - nop - nop - .endm +#define UART_SHIFT 2 +#include -- cgit v1.2.3-55-g7522 From 709eb502ebcfcca8a3a36bab3bca3bd78caa53b1 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 22 Mar 2006 20:14:11 +0000 Subject: [ARM] 3380/1: ixp2000: simplify ixdp2x00_master_npu() check Patch from Lennert Buytenhek On the IXDP2x00s, the NPU that is PCI master is always the egress (i.e. 'master') NPU. At least on the IXDP2800, both NPUs have flash, so the ixp2000_has_flash() check in ixdp2x00_master_npu() is useless. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/arch-ixp2000/ixdp2x00.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h index 229381c64283..546e2e8e27b8 100644 --- a/include/asm-arm/arch-ixp2000/ixdp2x00.h +++ b/include/asm-arm/arch-ixp2000/ixdp2x00.h @@ -72,12 +72,11 @@ #ifndef __ASSEMBLY__ /* - * Master NPU will always have flash and be PCI master. - * Slave NPU may or may not have flash but will never be PCI master. + * The master NPU is always PCI master. */ static inline unsigned int ixdp2x00_master_npu(void) { - return ((ixp2000_has_flash()) && (ixp2000_is_pcimaster())); + return !!ixp2000_is_pcimaster(); } /* -- cgit v1.2.3-55-g7522 From a04f2d9d3a08002a7712f18fcec43e2c4151d953 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 22 Mar 2006 20:14:11 +0000 Subject: [ARM] 3381/1: ixp2000: fix slowport write timing control register fields Patch from Lennert Buytenhek The original version of the chip docs had the PW and SU fields in the slowport write timing control register accidentally reversed. This is mentioned in the errata (documentation change #4) and fixed in newer docs. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/arch-ixp2000/ixp2000-regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h index 2b57f91b4ebd..ccae4bec92c5 100644 --- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h +++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h @@ -353,8 +353,8 @@ * Masks and shifts for various fields in the WTC and RTC registers. */ #define SLOWPORT_WRTC_MASK_HD 0x0003 -#define SLOWPORT_WRTC_MASK_SU 0x003c -#define SLOWPORT_WRTC_MASK_PW 0x03c0 +#define SLOWPORT_WRTC_MASK_PW 0x003c +#define SLOWPORT_WRTC_MASK_SU 0x03c0 #define SLOWPORT_WRTC_SHIFT_HD 0x00 #define SLOWPORT_WRTC_SHIFT_SU 0x02 -- cgit v1.2.3-55-g7522