// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) * * Copyright (C) 2019 Renesas Electronics Corp. */ /dts-v1/; #include "r8a774c0.dtsi" #include / { model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; compatible = "si-linux,cat874", "renesas,r8a774c0"; aliases { serial0 = &scif2; }; chosen { bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; }; vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1 1800000 0>; }; }; &extal_clk { clock-frequency = <48000000>; }; &pcie_bus_clk { clock-frequency = <100000000>; }; &pciec0 { /* Map all possible DDR as inbound ranges */ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; }; &pfc { scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; }; sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; power-source = <3300>; }; sdhi0_pins_uhs: sd0_uhs { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; power-source = <1800>; }; }; &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; status = "okay"; }; &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-1 = <&sdhi0_pins_uhs>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; bus-width = <4>; sd-uhs-sdr50; sd-uhs-sdr104; status = "okay"; };