/* SPDX-License-Identifier: GPL-2.0-only */ /* * ISH registers definitions * * Copyright (c) 2012-2016, Intel Corporation. */ #ifndef _ISHTP_ISH_REGS_H_ #define _ISHTP_ISH_REGS_H_ /*** IPC PCI Offsets and sizes ***/ /* ISH IPC Base Address */ #define IPC_REG_BASE 0x0000 /* Peripheral Interrupt Status Register */ #define IPC_REG_PISR_CHV_AB (IPC_REG_BASE + 0x00) /* Peripheral Interrupt Mask Register */ #define IPC_REG_PIMR_CHV_AB (IPC_REG_BASE + 0x04) /*BXT, CHV_K0*/ /*Peripheral Interrupt Status Register */ #define IPC_REG_PISR_BXT (IPC_REG_BASE + 0x0C) /*Peripheral Interrupt Mask Register */ #define IPC_REG_PIMR_BXT (IPC_REG_BASE + 0x08) /***********************************/ /* ISH Host Firmware status Register */ #define IPC_REG_ISH_HOST_FWSTS (IPC_REG_BASE + 0x34) /* Host Communication Register */ #define IPC_REG_HOST_COMM (IPC_REG_BASE + 0x38) /* Reset register */ #define IPC_REG_ISH_RST (IPC_REG_BASE + 0x44) /* Inbound doorbell register Host to ISH */ #define IPC_REG_HOST2ISH_DRBL (IPC_REG_BASE + 0x48) /* Outbound doorbell register ISH to Host */ #define IPC_REG_ISH2HOST_DRBL (IPC_REG_BASE + 0x54) /* ISH to HOST message registers */ #define IPC_REG_ISH2HOST_MSG (IPC_REG_BASE + 0x60) /* HOST to ISH message registers */ #define IPC_REG_HOST2ISH_MSG (IPC_REG_BASE + 0xE0) /* REMAP2 to enable DMA (D3 RCR) */ #define IPC_REG_ISH_RMP2 (IPC_REG_BASE + 0x368) #define IPC_REG_MAX (IPC_REG_BASE + 0x400) /*** register bits - HISR ***/ /* bit corresponds HOST2ISH interrupt in PISR and PIMR registers */ #define IPC_INT_HOST2ISH_BIT (1<<0) /***********************************/ /*CHV_A0, CHV_B0*/ /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */ #define IPC_INT_ISH2HOST_BIT_CHV_AB (1<<3) /*BXT, CHV_K0*/ /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */ #define IPC_INT_ISH2HOST_BIT_BXT (1<<0) /***********************************/ /* bit corresponds ISH2HOST busy clear interrupt in PIMR register */ #define IPC_INT_ISH2HOST_CLR_MASK_BIT (1<<11) /* offset of ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */ #define IPC_INT_ISH2HOST_CLR_OFFS (0) /* bit corresponds ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */ #define IPC_INT_ISH2HOST_CLR_BIT (1<> IPC_ISH_FWSTS_SHIFT) /* * FW status bits (relevant) */ #define IPC_FWSTS_ILUP 0x1 #define IPC_FWSTS_ISHTP_UP (1<<1) #define IPC_FWSTS_DMA0 (1<<16) #define IPC_FWSTS_DMA1 (1<<17) #define IPC_FWSTS_DMA2 (1<<18) #define IPC_FWSTS_DMA3 (1<<19) #define IPC_ISH_IN_DMA \ (IPC_FWSTS_DMA0 | IPC_FWSTS_DMA1 | IPC_FWSTS_DMA2 | IPC_FWSTS_DMA3) /* bit corresponds host ready bit in ISH FW Status Register */ #define IPC_ISH_ISHTP_READY_OFFS (1) #define IPC_ISH_ISHTP_READY_BIT (1<> IPC_HEADER_LENGTH_OFFSET)&IPC_HEADER_LENGTH_MASK) #define IPC_HEADER_GET_PROTOCOL(drbl_reg) \ (((drbl_reg) >> IPC_HEADER_PROTOCOL_OFFSET)&IPC_HEADER_PROTOCOL_MASK) #define IPC_HEADER_GET_MNG_CMD(drbl_reg) \ (((drbl_reg) >> IPC_HEADER_MNG_CMD_OFFSET)&IPC_HEADER_MNG_CMD_MASK) #define IPC_IS_BUSY(drbl_reg) \ (((drbl_reg)&IPC_DRBL_BUSY_BIT) == ((uint32_t)IPC_DRBL_BUSY_BIT)) /***********************************/ /*CHV_A0, CHV_B0*/ #define IPC_INT_FROM_ISH_TO_HOST_CHV_AB(drbl_reg) \ (((drbl_reg)&IPC_INT_ISH2HOST_BIT_CHV_AB) == \ ((u32)IPC_INT_ISH2HOST_BIT_CHV_AB)) /*BXT, CHV_K0*/ #define IPC_INT_FROM_ISH_TO_HOST_BXT(drbl_reg) \ (((drbl_reg)&IPC_INT_ISH2HOST_BIT_BXT) == \ ((u32)IPC_INT_ISH2HOST_BIT_BXT)) /***********************************/ #define IPC_BUILD_HEADER(length, protocol, busy) \ (((busy)<