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/*  linux/arch/arm/mach-pxa/xcep.c
 *
 *  Support for the Iskratel Electronics XCEP platform as used in
 *  the Libera instruments from Instrumentation Technologies.
 *
 *  Author:     Ales Bardorfer <ales@i-tech.si>
 *  Contributions by: Abbott, MG (Michael) <michael.abbott@diamond.ac.uk>
 *  Contributions by: Matej Kenda <matej.kenda@i-tech.si>
 *  Created:    June 2006
 *  Copyright:  (C) 2006-2009 Instrumentation Technologies
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/smc91x.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>

#include <mach/hardware.h>
#include <mach/pxa25x.h>
#include <mach/smemc.h>

#include "generic.h"

#define XCEP_ETH_PHYS		(PXA_CS3_PHYS + 0x00000300)
#define XCEP_ETH_PHYS_END	(PXA_CS3_PHYS + 0x000fffff)
#define XCEP_ETH_ATTR		(PXA_CS3_PHYS + 0x02000000)
#define XCEP_ETH_ATTR_END	(PXA_CS3_PHYS + 0x020fffff)
#define XCEP_ETH_IRQ		IRQ_GPIO0

/*  XCEP CPLD base */
#define XCEP_CPLD_BASE		0xf0000000


/* Flash partitions. */

static struct mtd_partition xcep_partitions[] = {
	{
		.name =		"Bootloader",
		.size =		0x00040000,
		.offset =	0,
		.mask_flags =	MTD_WRITEABLE
	}, {
		.name =		"Bootloader ENV",
		.size =		0x00040000,
		.offset =	0x00040000,
		.mask_flags =	MTD_WRITEABLE
	}, {
		.name =		"Kernel",
		.size =		0x00100000,
		.offset =	0x00080000,
	}, {
		.name =		"Rescue fs",
		.size =		0x00280000,
		.offset =	0x00180000,
	}, {
		.name =		"Filesystem",
		.size =		MTDPART_SIZ_FULL,
		.offset =	0x00400000
	}
};

static struct physmap_flash_data xcep_flash_data[] = {
	{
		.width		= 4,		/* bankwidth in bytes */
		.parts		= xcep_partitions,
		.nr_parts	= ARRAY_SIZE(xcep_partitions)
	}
};

static struct resource flash_resource = {
	.start	= PXA_CS0_PHYS,
	.end	= PXA_CS0_PHYS + SZ_32M - 1,
	.flags	= IORESOURCE_MEM,
};

static struct platform_device flash_device = {
	.name	= "physmap-flash",
	.id	= 0,
	.dev 	= {
		.platform_data = xcep_flash_data,
	},
	.resource = &flash_resource,
	.num_resources = 1,
};



/* SMC LAN91C111 network controller. */

static struct resource smc91x_resources[] = {
	[0] = {
		.name	= "smc91x-regs",
		.start	= XCEP_ETH_PHYS,
		.end	= XCEP_ETH_PHYS_END,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= XCEP_ETH_IRQ,
		.end	= XCEP_ETH_IRQ,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		.name	= "smc91x-attrib",
		.start	= XCEP_ETH_ATTR,
		.end	= XCEP_ETH_ATTR_END,
		.flags	= IORESOURCE_MEM,
	},
};

static struct smc91x_platdata xcep_smc91x_info = {
	.flags	= SMC91X_USE_32BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
	.dev		= {
		.platform_data = &xcep_smc91x_info,
	},
};


static struct platform_device *devices[] __initdata = {
	&flash_device,
	&smc91x_device,
};


/* We have to state that there are HWMON devices on the I2C bus on XCEP.
 * Drivers for HWMON verify capabilities of the adapter when loading and
 * refuse to attach if the adapter doesn't support HWMON class of devices.
 * See also Documentation/i2c/porting-clients. */
static struct i2c_pxa_platform_data xcep_i2c_platform_data  = {
	.class = I2C_CLASS_HWMON
};


static mfp_cfg_t xcep_pin_config[] __initdata = {
	GPIO79_nCS_3,	/* SMC 91C111 chip select. */
	GPIO80_nCS_4,	/* CPLD chip select. */
	/* SSP communication to MSP430 */
	GPIO23_SSP1_SCLK,
	GPIO24_SSP1_SFRM,
	GPIO25_SSP1_TXD,
	GPIO26_SSP1_RXD,
	GPIO27_SSP1_EXTCLK
};

static void __init xcep_init(void)
{
	pxa2xx_mfp_config(ARRAY_AND_SIZE(xcep_pin_config));

	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);
	pxa_set_hwuart_info(NULL);

	/* See Intel XScale Developer's Guide for details */
	/* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */
	__raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1);
	/* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */
	__raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2);

	platform_add_devices(ARRAY_AND_SIZE(devices));
	pxa_set_i2c_info(&xcep_i2c_platform_data);
}

MACHINE_START(XCEP, "Iskratel XCEP")
	.boot_params	= 0xa0000100,
	.init_machine	= xcep_init,
	.map_io		= pxa25x_map_io,
	.init_irq	= pxa25x_init_irq,
	.handle_irq	= pxa25x_handle_irq,
	.timer		= &pxa_timer,
MACHINE_END

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/*
 * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
 *
 * Copyright (C) 2009-2010 Texas Instruments, Inc.
 *
 * Benoit Cousson (b-cousson@ti.com)
 * Santosh Shilimkar (santosh.shilimkar@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H


/* Base address */
#define OMAP4_CTRL_MODULE_PAD_CORE				0x4a100000

/* Registers offset */
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION			0x0000
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO			0x0004
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG			0x0010
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0	0x01d8
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1	0x01dc
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2	0x01e0
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3	0x01e4
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4	0x01e8
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5	0x01ec
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6	0x01f0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL	0x05a0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE		0x05a4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0	0x05a8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1	0x05ac
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0	0x05b0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1	0x05b4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0	0x05b8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1	0x05bc
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2	0x05c0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC		0x05c4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS		0x05c8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE		0x0600
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0		0x0604
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX		0x0608
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC		0x060c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY		0x0610
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2			0x0614
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY		0x0618
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP		0x061c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE		0x0620
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1		0x0624
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1			0x0628
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI			0x062c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB			0x0630
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ			0x0634
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0		0x0638
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1		0x063c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2		0x0640
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3		0x0644
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0		0x0648
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1		0x064c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2		0x0650
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3		0x0654
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD		0x0658
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C			0x065c
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW	0x0660
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R		0x0664
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0	0x0668
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1		0x0700
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2		0x0704
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3		0x0708
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4		0x070c

/* Registers shifts and masks */

/* IP_REVISION */
#define OMAP4_IP_REV_SCHEME_SHIFT				30
#define OMAP4_IP_REV_SCHEME_MASK				(0x3 << 30)
#define OMAP4_IP_REV_FUNC_SHIFT					16
#define OMAP4_IP_REV_FUNC_MASK					(0xfff << 16)
#define OMAP4_IP_REV_RTL_SHIFT					11
#define OMAP4_IP_REV_RTL_MASK					(0x1f << 11)
#define OMAP4_IP_REV_MAJOR_SHIFT				8
#define OMAP4_IP_REV_MAJOR_MASK					(0x7 << 8)
#define OMAP4_IP_REV_CUSTOM_SHIFT				6
#define OMAP4_IP_REV_CUSTOM_MASK				(0x3 << 6)
#define OMAP4_IP_REV_MINOR_SHIFT				0
#define OMAP4_IP_REV_MINOR_MASK					(0x3f << 0)

/* IP_HWINFO */
#define OMAP4_IP_HWINFO_SHIFT					0
#define OMAP4_IP_HWINFO_MASK					(0xffffffff << 0)

/* IP_SYSCONFIG */
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT			2
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK			(0x3 << 2)

/* PADCONF_WAKEUPEVENT_0 */
#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT		31
#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK		(1 << 31)
#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT		30
#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK		(1 << 30)
#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT		29
#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK		(1 << 29)
#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT		28
#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK		(1 << 28)
#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT		27
#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK		(1 << 27)
#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT		26
#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK		(1 << 26)
#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT		25
#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK		(1 << 25)
#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT		24
#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK		(1 << 24)
#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT		23
#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK		(1 << 23)
#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT		22