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* disas/riscv.c: rvv: Add disas support for vector instructionsYang Liu2022-10-141-2/+1430
* target/riscv: Remove sideleg and sedelegRahul Pathak2022-09-261-2/+0Star
* target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot2022-09-071-6/+21
* disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructionsWeiwei Li2022-04-291-1/+172
* target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot2022-01-081-0/+5
* disas/riscv: Add Zb[abcs] instructionsPhilipp Tomsich2021-10-071-3/+154
* disas/riscv: Fix `rdinstreth` constraintWladimir J. van der Laan2019-06-271-2/+3
* disas/riscv: Disassemble reserved compressed encodings as illegalMichael Clark2019-06-271-17/+45
* disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster2019-04-181-1/+1
* RISC-V: Remove unnecessary disassembler constraintsMichael Clark2019-03-191-138/+0Star
* RISC-V: Fix missing break statement in disassemblerMichael Clark2018-05-061-1/+2
* RISC-V: Include instruction hex in disassemblyMichael Clark2018-05-061-19/+20
* RISC-V: Fix incorrect disassembly for addiwMichael Clark2018-03-281-1/+1
* RISC-V DisassemblerMichael Clark2018-03-061-0/+3048
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