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| author | Dylan Jhong | 2021-03-29 05:48:01 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-05-11 12:01:10 +0200 |
| commit | 01e723bf187974bd2b61cc6e936fa41d44fa16d2 (patch) | |
| tree | 09d7d81d19f309525227af7acad7501d026770e0 | |
| parent | docs/system/generic-loader.rst: Fix style (diff) | |
| download | qemu-01e723bf187974bd2b61cc6e936fa41d44fa16d2.tar.gz qemu-01e723bf187974bd2b61cc6e936fa41d44fa16d2.tar.xz qemu-01e723bf187974bd2b61cc6e936fa41d44fa16d2.zip | |
target/riscv: Align the data type of reset vector address
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong <dylan@andestech.com>
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210329034801.22667-1-dylan@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 86e7dbeb20..047d6344fe 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature) env->features |= (1ULL << feature); } -static void set_resetvec(CPURISCVState *env, int resetvec) +static void set_resetvec(CPURISCVState *env, target_ulong resetvec) { #ifndef CONFIG_USER_ONLY env->resetvec = resetvec; |