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| author | Peter Maydell | 2018-09-25 15:02:33 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-09-25 16:13:24 +0200 |
| commit | 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf (patch) | |
| tree | 408fe7d08c0dee09f520c3fd85f81143bf28c585 | |
| parent | aspeed/smc: fix some alignment issues (diff) | |
| download | qemu-060a65df056a5d6ca3a6a91e7bf150ca1fbccddf.tar.gz qemu-060a65df056a5d6ca3a6a91e7bf150ca1fbccddf.tar.xz qemu-060a65df056a5d6ca3a6a91e7bf150ca1fbccddf.zip | |
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
The ARMv8 architecture defines that an AArch32 CPU starts
in SVC mode, unless EL2 is the highest available EL, in
which case it starts in Hyp mode. (In ARMv7 a CPU with EL2
but not EL3 was not a valid configuration, but we don't
specifically reject this if the user asks for one.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20180823135047.16525-1-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/cpu.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 258ba6dcaa..b5e61cc177 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -199,8 +199,18 @@ static void arm_cpu_reset(CPUState *s) env->cp15.c15_cpar = 1; } #else - /* SVC mode with interrupts disabled. */ - env->uncached_cpsr = ARM_CPU_MODE_SVC; + + /* + * If the highest available EL is EL2, AArch32 will start in Hyp + * mode; otherwise it starts in SVC. Note that if we start in + * AArch64 then these values in the uncached_cpsr will be ignored. + */ + if (arm_feature(env, ARM_FEATURE_EL2) && + !arm_feature(env, ARM_FEATURE_EL3)) { + env->uncached_cpsr = ARM_CPU_MODE_HYP; + } else { + env->uncached_cpsr = ARM_CPU_MODE_SVC; + } env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; if (arm_feature(env, ARM_FEATURE_M)) { |