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| author | Richard Henderson | 2017-09-11 21:08:13 +0200 |
|---|---|---|
| committer | Richard Henderson | 2017-09-17 15:52:19 +0200 |
| commit | 07ddf036fa66bca279590c09fe1c46bcdcc5bcff (patch) | |
| tree | 22999ba8f57cc4da9f65b3db9a63653d82fe6891 | |
| parent | tcg: Remove tcg_regset_set (diff) | |
| download | qemu-07ddf036fa66bca279590c09fe1c46bcdcc5bcff.tar.gz qemu-07ddf036fa66bca279590c09fe1c46bcdcc5bcff.tar.xz qemu-07ddf036fa66bca279590c09fe1c46bcdcc5bcff.zip | |
tcg: Remove tcg_regset_{or,and,andnot,not}
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/tcg.c | 2 | ||||
| -rw-r--r-- | tcg/tcg.h | 4 |
2 files changed, 1 insertions, 5 deletions
@@ -2216,7 +2216,7 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs, TCGReg reg; TCGRegSet reg_ct; - tcg_regset_andnot(reg_ct, desired_regs, allocated_regs); + reg_ct = desired_regs & ~allocated_regs; order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; /* first try free registers */ @@ -190,10 +190,6 @@ typedef enum TCGOpcode { #define tcg_regset_set_reg(d, r) (d) |= 1L << (r) #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r)) #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) -#define tcg_regset_or(d, a, b) (d) = (a) | (b) -#define tcg_regset_and(d, a, b) (d) = (a) & (b) -#define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b) -#define tcg_regset_not(d, a) (d) = ~(a) #ifndef TCG_TARGET_INSN_UNIT_SIZE # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |