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| author | Philippe Mathieu-Daudé | 2020-12-08 19:01:01 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-01-14 17:13:53 +0100 |
| commit | 0e9524af2dd55bee8e10896a8579b29b7746efca (patch) | |
| tree | 2937a49892c7bc9cc6b723c86695fbc12596b933 | |
| parent | target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes (diff) | |
| download | qemu-0e9524af2dd55bee8e10896a8579b29b7746efca.tar.gz qemu-0e9524af2dd55bee8e10896a8579b29b7746efca.tar.xz qemu-0e9524af2dd55bee8e10896a8579b29b7746efca.zip | |
target/mips: Remove now unreachable LSA/DLSA opcodes code
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
| -rw-r--r-- | target/mips/translate.c | 28 |
1 files changed, 5 insertions, 23 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index d297029a77..e3bb1e83ef 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -280,9 +280,6 @@ enum { R6_OPC_DCLZ = 0x12 | OPC_SPECIAL, R6_OPC_DCLO = 0x13 | OPC_SPECIAL, R6_OPC_SDBBP = 0x0e | OPC_SPECIAL, - - OPC_LSA = 0x05 | OPC_SPECIAL, - OPC_DLSA = 0x15 | OPC_SPECIAL, }; /* Multiplication variants of the vr54xx. */ @@ -24318,9 +24315,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL(ctx->opcode); switch (op1) { - case OPC_LSA: - gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2)); - break; case OPC_MULT: case OPC_MULTU: case OPC_DIV: @@ -24371,9 +24365,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DLSA: - gen_dlsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2)); - break; case R6_OPC_DCLO: case R6_OPC_DCLZ: if (rt == 0 && sa == 1) { @@ -24635,18 +24626,14 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) check_insn(ctx, ISA_MIPS2); gen_trap(ctx, op1, rs, rt, -1); break; - case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { - decode_opc_special_r6(env, ctx); - } else { - /* Pmon entry point, also R4010 selsl */ + case OPC_PMON: + /* Pmon entry point, also R4010 selsl */ #ifdef MIPS_STRICT_STANDARD - MIPS_INVAL("PMON / selsl"); - gen_reserved_instruction(ctx); + MIPS_INVAL("PMON / selsl"); + gen_reserved_instruction(ctx); #else - gen_helper_0e0i(pmon, sa); + gen_helper_0e0i(pmon, sa); #endif - } break; case OPC_SYSCALL: generate_exception_end(ctx, EXCP_SYSCALL); @@ -24737,11 +24724,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) break; } break; - case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { - decode_opc_special_r6(env, ctx); - } - break; #endif default: if (ctx->insn_flags & ISA_MIPS_R6) { |