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| author | Stafford Horne | 2022-06-12 11:59:34 +0200 |
|---|---|---|
| committer | Stafford Horne | 2022-09-04 08:02:56 +0200 |
| commit | 0fd8a106efb6bc2e55b3e9629b106d13a7214570 (patch) | |
| tree | 8be95e66612b64b611cb20fc9353797aa0470a88 | |
| parent | hw/openrisc: Split re-usable boot time apis out to boot.c (diff) | |
| download | qemu-0fd8a106efb6bc2e55b3e9629b106d13a7214570.tar.gz qemu-0fd8a106efb6bc2e55b3e9629b106d13a7214570.tar.xz qemu-0fd8a106efb6bc2e55b3e9629b106d13a7214570.zip | |
target/openrisc: Fix memory reading in debugger
In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and
instruction TLB reads were combined. This, broke debugger reads where
we first tried to map using the data tlb then fall back to the
instruction tlb.
This patch replicates this logic by first requesting a PAGE_READ
protection mapping then falling back to PAGE_EXEC.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
| -rw-r--r-- | target/openrisc/mmu.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index d7e1320998..0b8afdbacf 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -148,7 +148,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) case SR_DME | SR_IME: /* The mmu is definitely enabled. */ excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, - PAGE_EXEC | PAGE_READ | PAGE_WRITE, + PAGE_READ, + (sr & SR_SM) != 0); + if (!excp) { + return phys_addr; + } + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, + PAGE_EXEC, (sr & SR_SM) != 0); return excp ? -1 : phys_addr; |