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| author | Richard Henderson | 2020-09-08 02:47:31 +0200 |
|---|---|---|
| committer | Richard Henderson | 2021-01-13 19:39:08 +0100 |
| commit | 10061ffe56998ffe9ab6b83ee8338673fa280ca7 (patch) | |
| tree | 84d4c5078809a5451fa8aab3e442c4879c6543dc | |
| parent | tcg/ppc: Use tcg_constant_vec with tcg vec expanders (diff) | |
| download | qemu-10061ffe56998ffe9ab6b83ee8338673fa280ca7.tar.gz qemu-10061ffe56998ffe9ab6b83ee8338673fa280ca7.tar.xz qemu-10061ffe56998ffe9ab6b83ee8338673fa280ca7.zip | |
tcg/aarch64: Use tcg_constant_vec with tcg vec expanders
Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to
"t1 = -v2, t2 = c - v2". This avoids a serial dependency
between t1 and t2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/aarch64/tcg-target.c.inc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index e370b7e61c..23954ec7cf 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2516,7 +2516,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t1, t2; + TCGv_vec v0, v1, v2, t1, t2, c1; TCGArg a2; va_start(va, a0); @@ -2548,8 +2548,8 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotlv_vec: t1 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(vece, t1, 8 << vece); - tcg_gen_sub_vec(vece, t1, v2, t1); + c1 = tcg_constant_vec(type, vece, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, c1); /* Right shifts are negative left shifts for AArch64. */ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t1)); @@ -2562,9 +2562,9 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotrv_vec: t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); + c1 = tcg_constant_vec(type, vece, 8 << vece); tcg_gen_neg_vec(vece, t1, v2); - tcg_gen_dupi_vec(vece, t2, 8 << vece); - tcg_gen_add_vec(vece, t2, t1, t2); + tcg_gen_sub_vec(vece, t2, c1, v2); /* Right shifts are negative left shifts for AArch64. */ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t1)); |