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| author | Guenter Roeck | 2014-04-25 17:39:47 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias | 2014-05-13 01:12:40 +0200 |
| commit | 12f7fb60863f5aae44fa7a6c1f52cbecd29d4e9c (patch) | |
| tree | fae9729b76d18aef6fbe814fc647ba5b93fe0d0e | |
| parent | microblaze: Respect the reset vector (diff) | |
| download | qemu-12f7fb60863f5aae44fa7a6c1f52cbecd29d4e9c.tar.gz qemu-12f7fb60863f5aae44fa7a6c1f52cbecd29d4e9c.tar.xz qemu-12f7fb60863f5aae44fa7a6c1f52cbecd29d4e9c.zip | |
xilinx_intc: Fix writes into MER register
The MER register only has two valid bits. This is now used by
the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
and later to hang when run under qemu-microblaze. Mask valid bits before
writing the register to solve the problem.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Edgar: Untabified]
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
| -rw-r--r-- | hw/intc/xilinx_intc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 1b228ff4e0..c3682f1b20 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -121,6 +121,9 @@ pic_write(void *opaque, hwaddr addr, case R_CIE: p->regs[R_IER] &= ~value; /* Atomic clear ie. */ break; + case R_MER: + p->regs[R_MER] = value & 0x3; + break; case R_ISR: if ((p->regs[R_MER] & 2)) { break; |