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| author | Michael S. Tsirkin | 2013-09-28 23:09:35 +0200 |
|---|---|---|
| committer | Kevin Wolf | 2013-10-11 16:49:59 +0200 |
| commit | 13164591f30ad95ae24f9892cf2caf779271a29b (patch) | |
| tree | 8c7c0c5235f7883e149150488f442b699cac441d | |
| parent | qemu-iotests: Discard preallocated zero clusters (diff) | |
| download | qemu-13164591f30ad95ae24f9892cf2caf779271a29b.tar.gz qemu-13164591f30ad95ae24f9892cf2caf779271a29b.tar.xz qemu-13164591f30ad95ae24f9892cf2caf779271a29b.zip | |
ahci: set ahci mode on reset
ATM we set AHCI mode on 1st GHC write.
Spec says we should set it on reset.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| -rw-r--r-- | hw/ide/ahci.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index a71a4ca47c..a8be62cf99 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1198,7 +1198,15 @@ void ahci_reset(AHCIState *s) int i; s->control_regs.irqstatus = 0; - s->control_regs.ghc = 0; + /* AHCI Enable (AE) + * The implementation of this bit is dependent upon the value of the + * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and + * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be + * read-only and shall have a reset value of '1'. + * + * We set HOST_CAP_AHCI so we must enable AHCI at reset. + */ + s->control_regs.ghc = HOST_CTL_AHCI_EN; for (i = 0; i < s->ports; i++) { pr = &s->dev[i].port_regs; |