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| author | Taylor Simpson | 2021-05-18 23:45:18 +0200 |
|---|---|---|
| committer | Taylor Simpson | 2021-11-03 22:01:29 +0100 |
| commit | 144da35776e33a25c7783b6b04ed77e375b1c87c (patch) | |
| tree | 7b28ccf529aee8e2ad560c545024f9a971c719ed | |
| parent | Hexagon HVX (target/hexagon) import macro definitions (diff) | |
| download | qemu-144da35776e33a25c7783b6b04ed77e375b1c87c.tar.gz qemu-144da35776e33a25c7783b6b04ed77e375b1c87c.tar.xz qemu-144da35776e33a25c7783b6b04ed77e375b1c87c.zip | |
Hexagon HVX (target/hexagon) semantics generator
Add HVX support to the semantics generator
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| -rw-r--r-- | target/hexagon/gen_semantics.c | 33 | ||||
| -rwxr-xr-x | target/hexagon/hex_common.py | 13 |
2 files changed, 46 insertions, 0 deletions
diff --git a/target/hexagon/gen_semantics.c b/target/hexagon/gen_semantics.c index c5fccecc9e..4a2bdd70e9 100644 --- a/target/hexagon/gen_semantics.c +++ b/target/hexagon/gen_semantics.c @@ -44,6 +44,11 @@ int main(int argc, char *argv[]) * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), * "Add 32-bit registers", * { RdV=RsV+RtV;}) + * HVX instructions have the following form + * EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)", + * ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX), + * "Insert Word Scalar into Vector", + * VxV.uw[0] = RtV;) */ #define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ do { \ @@ -59,8 +64,23 @@ int main(int argc, char *argv[]) ")\n", \ #TAG, STRINGIZE(ATTRIBS)); \ } while (0); +#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + do { \ + fprintf(outfile, "SEMANTICS( \\\n" \ + " \"%s\", \\\n" \ + " %s, \\\n" \ + " \"\"\"%s\"\"\" \\\n" \ + ")\n", \ + #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ + fprintf(outfile, "ATTRIBUTES( \\\n" \ + " \"%s\", \\\n" \ + " \"%s\" \\\n" \ + ")\n", \ + #TAG, STRINGIZE(ATTRIBS)); \ + } while (0); #include "imported/allidefs.def" #undef Q6INSN +#undef EXTINSN /* * Process the macro definitions @@ -83,6 +103,19 @@ int main(int argc, char *argv[]) #include "imported/macros.def" #undef DEF_MACRO +/* + * Process the macros for HVX + */ +#define DEF_MACRO(MNAME, BEH, ATTRS) \ + fprintf(outfile, "MACROATTRIB( \\\n" \ + " \"%s\", \\\n" \ + " \"\"\"%s\"\"\", \\\n" \ + " \"%s\" \\\n" \ + ")\n", \ + #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); +#include "imported/allext_macros.def" +#undef DEF_MACRO + fclose(outfile); return 0; } diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index a84b003f7e..c81aca8d2a 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -145,6 +145,9 @@ def compute_tag_immediates(tag): ## P predicate register ## R GPR register ## M modifier register +## Q HVX predicate vector +## V HVX vector register +## O HVX new vector register ## regid can be one of the following ## d, e destination register ## dd destination register pair @@ -180,6 +183,9 @@ def is_readwrite(regid): def is_scalar_reg(regtype): return regtype in "RPC" +def is_hvx_reg(regtype): + return regtype in "VQ" + def is_old_val(regtype, regid, tag): return regtype+regid+'V' in semdict[tag] @@ -203,6 +209,13 @@ def need_ea(tag): def skip_qemu_helper(tag): return tag in overrides.keys() +def is_tmp_result(tag): + return ('A_CVI_TMP' in attribdict[tag] or + 'A_CVI_TMP_DST' in attribdict[tag]) + +def is_new_result(tag): + return ('A_CVI_NEW' in attribdict[tag]) + def imm_name(immlett): return "%siV" % immlett |