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| author | Klaus Jensen | 2020-11-13 09:50:33 +0100 |
|---|---|---|
| committer | Klaus Jensen | 2021-02-08 21:15:53 +0100 |
| commit | 1901b4967c3fdd47e59d9023aea2285d94f3998a (patch) | |
| tree | 2a11540c20dd5662b2a0e167b91320bc42a04d21 | |
| parent | hw/block/nvme: indicate CMB support through controller capabilities register (diff) | |
| download | qemu-1901b4967c3fdd47e59d9023aea2285d94f3998a.tar.gz qemu-1901b4967c3fdd47e59d9023aea2285d94f3998a.tar.xz qemu-1901b4967c3fdd47e59d9023aea2285d94f3998a.zip | |
hw/block/nvme: move msix table and pba to BAR 0
In the interest of supporting both CMB and PMR to be enabled on the same
device, move the MSI-X table and pending bit array out of BAR 4 and into
BAR 0.
This is a simplified version of the patch contributed by Andrzej
Jakowski (see [1]). Leaving the CMB at offset 0 removes the need for
changes to CMB address mapping code.
[1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-3-andrzej.jakowski@linux.intel.com/
Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com>
Tested-by: Minwoo Im <minwoo.im.dev@gmail.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
| -rw-r--r-- | hw/block/nvme.c | 23 | ||||
| -rw-r--r-- | hw/block/nvme.h | 1 |
2 files changed, 22 insertions, 2 deletions
diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 5f12ac1200..85d3c43c4f 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -4268,6 +4268,8 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { uint8_t *pci_conf = pci_dev->config; + uint64_t bar_size, msix_table_size, msix_pba_size; + unsigned msix_table_offset, msix_pba_offset; int ret; Error *err = NULL; @@ -4286,11 +4288,28 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); + bar_size = QEMU_ALIGN_UP(n->reg_size, 4 * KiB); + msix_table_offset = bar_size; + msix_table_size = PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize; + + bar_size += msix_table_size; + bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB); + msix_pba_offset = bar_size; + msix_pba_size = QEMU_ALIGN_UP(n->params.msix_qsize, 64) / 8; + + bar_size += msix_pba_size; + bar_size = pow2ceil(bar_size); + + memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); + memory_region_add_subregion(&n->bar0, 0, &n->iomem); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | - PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - ret = msix_init_exclusive_bar(pci_dev, n->params.msix_qsize, 4, &err); + PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0); + ret = msix_init(pci_dev, n->params.msix_qsize, + &n->bar0, 0, msix_table_offset, + &n->bar0, 0, msix_pba_offset, 0, &err); if (ret < 0) { if (ret == -ENOTSUP) { warn_report_err(err); diff --git a/hw/block/nvme.h b/hw/block/nvme.h index b0d5b6409d..1cdb360bc5 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -125,6 +125,7 @@ typedef struct NvmeFeatureVal { typedef struct NvmeCtrl { PCIDevice parent_obj; + MemoryRegion bar0; MemoryRegion iomem; MemoryRegion ctrl_mem; NvmeBar bar; |