diff options
| author | Stefan Hajnoczi | 2018-08-16 15:05:28 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-16 15:05:28 +0200 |
| commit | 191776b96a381b5d2b8d3f90c1c02b3e4779e5f7 (patch) | |
| tree | 44eb735b59abc889edaf06feea0b865482bb12c7 | |
| parent | hw/arm: make bitbanded IO optional on ARMv7-M (diff) | |
| download | qemu-191776b96a381b5d2b8d3f90c1c02b3e4779e5f7.tar.gz qemu-191776b96a381b5d2b8d3f90c1c02b3e4779e5f7.tar.xz qemu-191776b96a381b5d2b8d3f90c1c02b3e4779e5f7.zip | |
target/arm: add "cortex-m0" CPU model
Define a "cortex-m0" ARMv6-M CPU model.
Most of the register reset values set by other CPU models are not
relevant for the cut-down ARMv6-M architecture.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180814162739.11814-3-stefanha@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a4d46db13a..258ba6dcaa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1255,6 +1255,15 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr = 1; } +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + cpu->midr = 0x410cc200; +} + static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -1845,6 +1854,8 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm1136", .initfn = arm1136_initfn }, { .name = "arm1176", .initfn = arm1176_initfn }, { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, + { .name = "cortex-m0", .initfn = cortex_m0_initfn, + .class_init = arm_v7m_class_init }, { .name = "cortex-m3", .initfn = cortex_m3_initfn, .class_init = arm_v7m_class_init }, { .name = "cortex-m4", .initfn = cortex_m4_initfn, |