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| author | Xiaoyao Li | 2020-07-16 10:20:18 +0200 |
|---|---|---|
| committer | Paolo Bonzini | 2020-09-30 19:09:20 +0200 |
| commit | 19ca8285fcd61a8f60f2f44f789a561e0958e8e6 (patch) | |
| tree | 2302869c6262222274ee478c130d9e723d6e443c | |
| parent | hw: megasas: consider 'iov_count=0' is an error in megasas_map_sgl (diff) | |
| download | qemu-19ca8285fcd61a8f60f2f44f789a561e0958e8e6.tar.gz qemu-19ca8285fcd61a8f60f2f44f789a561e0958e8e6.tar.xz qemu-19ca8285fcd61a8f60f2f44f789a561e0958e8e6.zip | |
i386/cpu: Clear FEAT_XSAVE_COMP_{LO,HI} when XSAVE is not available
Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the
processor provides no further enumeration through CPUID function 0DH.
QEMU does not do this for "-cpu host,-xsave".
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20200716082019.215316-2-xiaoyao.li@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0ea0630e1f..f37eb7b675 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6267,6 +6267,8 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu) uint64_t mask; if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { + env->features[FEAT_XSAVE_COMP_LO] = 0; + env->features[FEAT_XSAVE_COMP_HI] = 0; return; } |