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| author | Bin Meng | 2021-01-29 14:23:14 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-02-02 18:00:54 +0100 |
| commit | 1da79ecc7a299a6f3633876c8e49e5418ae37fcf (patch) | |
| tree | f6d59c2791a7087e770a016283f66cadfe08d1b3 | |
| parent | hw/arm/smmuv3: Fix addr_mask for range-based invalidation (diff) | |
| download | qemu-1da79ecc7a299a6f3633876c8e49e5418ae37fcf.tar.gz qemu-1da79ecc7a299a6f3633876c8e49e5418ae37fcf.tar.xz qemu-1da79ecc7a299a6f3633876c8e49e5418ae37fcf.zip | |
hw/ssi: imx_spi: Use a macro for number of chip selects supported
Avoid using a magic number (4) everywhere for the number of chip
selects supported.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-id: 20210129132323.30946-2-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/ssi/imx_spi.c | 4 | ||||
| -rw-r--r-- | include/hw/ssi/imx_spi.h | 5 |
2 files changed, 6 insertions, 3 deletions
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454..e605049a21 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f364..eeaf49bbac 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; |