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| author | Jonathan Behrens | 2019-05-08 19:38:35 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:25 +0200 |
| commit | 1e0d985fa9136a563168a3da66f3d17820404ee2 (patch) | |
| tree | edfeec3a5ef58a435424087a9cfa8f5020429127 | |
| parent | target/riscv: More accurate handling of `sip` CSR (diff) | |
| download | qemu-1e0d985fa9136a563168a3da66f3d17820404ee2.tar.gz qemu-1e0d985fa9136a563168a3da66f3d17820404ee2.tar.xz qemu-1e0d985fa9136a563168a3da66f3d17820404ee2.zip | |
target/riscv: Only flush TLB if SATP.ASID changes
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| -rw-r--r-- | target/riscv/csr.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0f51c7eae2..f9e2910643 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { return -1; } else { - tlb_flush(CPU(riscv_env_get_cpu(env))); + if((val ^ env->satp) & SATP_ASID) { + tlb_flush(CPU(riscv_env_get_cpu(env))); + } env->satp = val; } } |