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| author | Rémi Denis-Courmont | 2021-01-12 11:45:10 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:52 +0100 |
| commit | 24179fea7e34c4952d4878ae1b26108ba65e5933 (patch) | |
| tree | 6560f87cab40d8e936238074578768d1068730bc | |
| parent | target/arm: Implement SCR_EL2.EEL2 (diff) | |
| download | qemu-24179fea7e34c4952d4878ae1b26108ba65e5933.tar.gz qemu-24179fea7e34c4952d4878ae1b26108ba65e5933.tar.xz qemu-24179fea7e34c4952d4878ae1b26108ba65e5933.zip | |
target/arm: enable Secure EL2 in max CPU
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-18-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dbd06ccc24..5e851028c5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -665,6 +665,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; |