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| author | Peter Maydell | 2021-06-17 14:15:49 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-06-21 18:12:50 +0200 |
| commit | 249b5309c44831555b7fb6dab68d7a6f9f573882 (patch) | |
| tree | e0d4a97faf1276a3390b8d9d6d950bd20a245f5c | |
| parent | target/arm: Implement MVE VCLS (diff) | |
| download | qemu-249b5309c44831555b7fb6dab68d7a6f9f573882.tar.gz qemu-249b5309c44831555b7fb6dab68d7a6f9f573882.tar.xz qemu-249b5309c44831555b7fb6dab68d7a6f9f573882.zip | |
target/arm: Implement MVE VREV16, VREV32, VREV64
Implement the MVE instructions VREV16, VREV32 and VREV64.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-6-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/helper-mve.h | 7 | ||||
| -rw-r--r-- | target/arm/mve.decode | 4 | ||||
| -rw-r--r-- | target/arm/mve_helper.c | 7 | ||||
| -rw-r--r-- | target/arm/translate-mve.c | 33 |
4 files changed, 51 insertions, 0 deletions
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index bdd6675ea1..4c89387587 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -40,3 +40,10 @@ DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vrev16b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev32b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index adceef9159..16ee511a5c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -70,3 +70,7 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op + +VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op +VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op +VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index ba01ea3bcd..8b565b50a9 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -270,3 +270,10 @@ DO_1OP(vclsw, 4, int32_t, clrsb32) DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) DO_1OP(vclzw, 4, uint32_t, clz32) + +DO_1OP(vrev16b, 2, uint16_t, bswap16) +DO_1OP(vrev32b, 4, uint32_t, bswap32) +DO_1OP(vrev32h, 4, uint32_t, hswap32) +DO_1OP(vrev64b, 8, uint64_t, bswap64) +DO_1OP(vrev64h, 8, uint64_t, hswap64) +DO_1OP(vrev64w, 8, uint64_t, wswap64) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4e5d032242..32a8324c5e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -199,3 +199,36 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) DO_1OP(VCLZ, vclz) DO_1OP(VCLS, vcls) + +static bool trans_VREV16(DisasContext *s, arg_1op *a) +{ + static MVEGenOneOpFn * const fns[] = { + gen_helper_mve_vrev16b, + NULL, + NULL, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} + +static bool trans_VREV32(DisasContext *s, arg_1op *a) +{ + static MVEGenOneOpFn * const fns[] = { + gen_helper_mve_vrev32b, + gen_helper_mve_vrev32h, + NULL, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} + +static bool trans_VREV64(DisasContext *s, arg_1op *a) +{ + static MVEGenOneOpFn * const fns[] = { + gen_helper_mve_vrev64b, + gen_helper_mve_vrev64h, + gen_helper_mve_vrev64w, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} |