diff options
| author | Paul A. Clarke | 2019-08-21 17:28:41 +0200 |
|---|---|---|
| committer | David Gibson | 2019-08-29 01:46:07 +0200 |
| commit | 256be7d07a0c1f9d8e2076aa4f7ca4fc048f6838 (patch) | |
| tree | d6b809a78731190fdf6cad9f440a1a104e1b52f8 | |
| parent | tests/boot-serial-test: add support for all the PowerNV machines (diff) | |
| download | qemu-256be7d07a0c1f9d8e2076aa4f7ca4fc048f6838.tar.gz qemu-256be7d07a0c1f9d8e2076aa4f7ca4fc048f6838.tar.xz qemu-256be7d07a0c1f9d8e2076aa4f7ca4fc048f6838.zip | |
ppc: Fix xsmaddmdp and friends
A class of instructions of the form:
op Target,A,B
which operate like:
Target = Target * A + B
have a bit set which distinguishes them from instructions that operate as:
Target = Target * B + A
This bit is not being checked properly (using PPC_BIT macro), so all
instructions in this class are operating incorrectly as the second form
above. The bit was being checked as if it were part of a 64-bit
instruction opcode, rather than a proper 32-bit opcode. Fix by using the
macro (PPC_BIT32) which treats the opcode as a 32-bit quantity.
Fixes: c9f4e4d8b632 ("target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro")
Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
Message-Id: <1566401321-22419-1-git-send-email-pc@us.ibm.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Tested-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | target/ppc/translate/vsx-impl.inc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 3922686ad6..8287e272f5 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1308,7 +1308,7 @@ static void gen_##name(DisasContext *ctx) \ } \ xt = gen_vsr_ptr(xT(ctx->opcode)); \ xa = gen_vsr_ptr(xA(ctx->opcode)); \ - if (ctx->opcode & PPC_BIT(25)) { \ + if (ctx->opcode & PPC_BIT32(25)) { \ /* \ * AxT + B \ */ \ |