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authorArtyom Tarasenko2014-08-08 22:48:00 +0200
committerMark Cave-Ayland2014-08-17 14:24:27 +0200
commit2a5fade753e66ae68f0131962391cd78b99afa53 (patch)
treebda399b95595836f74d1b113883eb82f9bad03c7
parentapb: add IOMMU flush register implementation (diff)
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target-sparc64: implement Short Floating-Point Store Instructions
Implement Short Floating-Point Store Instructions as described in the chapter 13.5.2 of UltraSPARC-IIi User's Manual. Particularly this instructions are used by NetBSD 4.0.1+ /sparc64 Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
-rw-r--r--target-sparc/ldst_helper.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 03bd9f9706..1a62e193bd 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2154,7 +2154,6 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
unsigned int i;
target_ulong val;
- helper_check_align(env, addr, 3);
addr = asi_address_mask(env, asi, addr);
switch (asi) {
@@ -2192,7 +2191,21 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
}
return;
+ case 0xd2: /* 16-bit floating point load primary */
+ case 0xd3: /* 16-bit floating point load secondary */
+ case 0xda: /* 16-bit floating point load primary, LE */
+ case 0xdb: /* 16-bit floating point load secondary, LE */
+ helper_check_align(env, addr, 1);
+ /* Fall through */
+ case 0xd0: /* 8-bit floating point load primary */
+ case 0xd1: /* 8-bit floating point load secondary */
+ case 0xd8: /* 8-bit floating point load primary, LE */
+ case 0xd9: /* 8-bit floating point load secondary, LE */
+ val = env->fpr[rd / 2].l.lower;
+ helper_st_asi(env, addr, val, asi & 0x8d, ((asi & 2) >> 1) + 1);
+ return;
default:
+ helper_check_align(env, addr, 3);
break;
}