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| author | Richard Henderson | 2020-06-26 05:31:38 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-06-26 15:31:12 +0200 |
| commit | 34669338bd9d66255fceaa84c314251ca49ca8d5 (patch) | |
| tree | e8a9a403cfb711dcbe8ab266696447d851ab5d5f | |
| parent | target/arm: Implement data cache set allocation tags (diff) | |
| download | qemu-34669338bd9d66255fceaa84c314251ca49ca8d5.tar.gz qemu-34669338bd9d66255fceaa84c314251ca49ca8d5.tar.xz qemu-34669338bd9d66255fceaa84c314251ca49ca8d5.zip | |
target/arm: Set PSTATE.TCO on exception entry
D1.10 specifies that exception handlers begin with tag checks overridden.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-41-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 23cf44fcf4..d220612a20 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9704,6 +9704,9 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) break; } } + if (cpu_isar_feature(aa64_mte, cpu)) { + new_mode |= PSTATE_TCO; + } pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; |