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| author | Richard Henderson | 2020-07-24 02:28:03 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-08-22 07:37:55 +0200 |
| commit | 40eaa473611936445ae9c63841445cfa6e36840b (patch) | |
| tree | cf73eb4a713f27e117553111a5a6ec77968698da | |
| parent | target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s (diff) | |
| download | qemu-40eaa473611936445ae9c63841445cfa6e36840b.tar.gz qemu-40eaa473611936445ae9c63841445cfa6e36840b.tar.xz qemu-40eaa473611936445ae9c63841445cfa6e36840b.zip | |
target/riscv: Generate nanboxed results from trans_rvf.inc.c
Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/insn_trans/trans_rvf.c.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index c7057482e8..264d3139f1 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], 0, 31); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); tcg_temp_free_i64(t0); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); tcg_temp_free_i64(t0); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) #else tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); #endif + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); tcg_temp_free(t0); |