diff options
| author | Palmer Dabbelt | 2022-07-14 20:00:33 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-07-27 09:34:02 +0200 |
| commit | 44602af8585fd2f331c69e2c071eff39227535ed (patch) | |
| tree | fd0b285cf73a5acb62fa67c411fa304df2baa95a | |
| parent | Update version for v7.1.0-rc0 release (diff) | |
| download | qemu-44602af8585fd2f331c69e2c071eff39227535ed.tar.gz qemu-44602af8585fd2f331c69e2c071eff39227535ed.tar.xz qemu-44602af8585fd2f331c69e2c071eff39227535ed.zip | |
RISC-V: Allow both Zmmul and M
We got to talking about how Zmmul and M interact with each other
https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
combination, it just means that the multiplication instructions are
supported even when M is disabled at runtime via misa.
This just stops overriding M from Zmmul, with that the other checks for
the multiplication instructions work as per the ISA.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220714180033.22385-1-palmer@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bb3973806..ac6f82ebd0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -619,11 +619,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_ifencei = true; } - if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) { - warn_report("Zmmul will override M"); - cpu->cfg.ext_m = false; - } - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); |