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| author | Prasad J Pandit | 2020-08-11 13:41:26 +0200 |
|---|---|---|
| committer | Paolo Bonzini | 2021-02-08 15:15:32 +0100 |
| commit | 4f2a5202a05fc1612954804a2482f07bff105ea2 (patch) | |
| tree | b53d10fd2fd6ed9c3cfc059783c318de80b57174 | |
| parent | hw/pci-host: add pci-intack write method (diff) | |
| download | qemu-4f2a5202a05fc1612954804a2482f07bff105ea2.tar.gz qemu-4f2a5202a05fc1612954804a2482f07bff105ea2.tar.xz qemu-4f2a5202a05fc1612954804a2482f07bff105ea2.zip | |
pci-host: designware: add pcie-msi read method
Add pcie-msi mmio read method to avoid NULL pointer dereference
issue.
Reported-by: Lei Sun <slei.casper@gmail.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Message-Id: <20200811114133.672647-3-ppandit@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | hw/pci-host/designware.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index f9fb97a3e3..bde3a343a2 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "hw/pci/msi.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" @@ -63,6 +64,23 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root) return DESIGNWARE_PCIE_HOST(bus->parent); } +static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, + unsigned size) +{ + /* + * Attempts to read from the MSI address are undefined in + * the PCI specifications. For this hardware, the datasheet + * specifies that a read from the magic address is simply not + * intercepted by the MSI controller, and will go out to the + * AHB/AXI bus like any other PCI-device-initiated DMA read. + * This is not trivial to implement in QEMU, so since + * well-behaved guests won't ever ask a PCI device to DMA from + * this address we just log the missing functionality. + */ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); + return 0; +} + static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -77,6 +95,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, } static const MemoryRegionOps designware_pci_host_msi_ops = { + .read = designware_pcie_root_msi_read, .write = designware_pcie_root_msi_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { |