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| author | Xuzhou Cheng | 2021-01-29 14:23:20 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-02-02 18:00:55 +0100 |
| commit | 50dc25932eb31fca15104968e596b7035ce9ece1 (patch) | |
| tree | f905c0048b436c4a334c33d774b57736b802320d | |
| parent | hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled (diff) | |
| download | qemu-50dc25932eb31fca15104968e596b7035ce9ece1.tar.gz qemu-50dc25932eb31fca15104968e596b7035ce9ece1.tar.xz qemu-50dc25932eb31fca15104968e596b7035ce9ece1.zip | |
hw/ssi: imx_spi: Disable chip selects when controller is disabled
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_soft_reset() is called to reset the controller, but chip
select lines should have been disabled, otherwise the state machine
of any devices (e.g.: SPI flashes) connected to the SPI master is
stuck to its last state and responds incorrectly to any follow-up
commands.
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210129132323.30946-8-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/ssi/imx_spi.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4cfbb73e35..2fb65498c3 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -254,9 +254,15 @@ static void imx_spi_common_reset(IMXSPIState *s) static void imx_spi_soft_reset(IMXSPIState *s) { + int i; + imx_spi_common_reset(s); imx_spi_update_irq(s); + + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static void imx_spi_reset(DeviceState *dev) |