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| author | Alistair Francis | 2020-12-16 19:22:51 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:44 +0100 |
| commit | 51ae0cabc67c418264d5ae28214603aabc88b9b6 (patch) | |
| tree | edcd10c7796f5f207f62f22b9f2320b48d1e9cd7 | |
| parent | target/riscv: fpu_helper: Match function defs in HELPER macros (diff) | |
| download | qemu-51ae0cabc67c418264d5ae28214603aabc88b9b6.tar.gz qemu-51ae0cabc67c418264d5ae28214603aabc88b9b6.tar.xz qemu-51ae0cabc67c418264d5ae28214603aabc88b9b6.zip | |
target/riscv: Add a riscv_cpu_is_32bit() helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
| -rw-r--r-- | target/riscv/cpu.c | 9 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 2 |
2 files changed, 11 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a0264fc6b..32a6916b8a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -108,6 +108,15 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } +bool riscv_cpu_is_32bit(CPURISCVState *env) +{ + if (env->misa & RV64) { + return false; + } + + return true; +} + static void set_misa(CPURISCVState *env, target_ulong misa) { env->misa_mask = env->misa = misa; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9c064f3094..6339e84819 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -384,6 +384,8 @@ FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +bool riscv_cpu_is_32bit(CPURISCVState *env); + /* * A simplification for VLMAX * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) |