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| author | aurel32 | 2009-03-07 23:10:28 +0100 |
|---|---|---|
| committer | aurel32 | 2009-03-07 23:10:28 +0100 |
| commit | 533d177a98c5f73ba34fd04bf232fac1f44cf168 (patch) | |
| tree | 81e34aaf24b7e726cf6601c2f8b240088e000147 | |
| parent | Work around QEMU GDB stub suboptimality (diff) | |
| download | qemu-533d177a98c5f73ba34fd04bf232fac1f44cf168.tar.gz qemu-533d177a98c5f73ba34fd04bf232fac1f44cf168.tar.xz qemu-533d177a98c5f73ba34fd04bf232fac1f44cf168.zip | |
Fix correct reset value for ARM CP15 c1 auxiliary control register
According to ARM Cortex A8 Technical Reference Manual, the reset value for CP15 c1 auxiliary control
register is 2, not zero (page 3.12).
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6771 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-arm/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index d6362ca4ad..34641428df 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1694,7 +1694,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) case ARM_CPUID_ARM11MPCORE: return 1; case ARM_CPUID_CORTEXA8: - return 0; + return 2; default: goto bad_reg; } |