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authorPeer Adelt2016-06-07 17:49:14 +0200
committerBastian Koppelmann2017-01-11 14:37:15 +0100
commit550929dd4622f8e2b1b5c277f32089d83cb1e595 (patch)
tree774453418b3d1bca5090cf2bfa39fe769a07f6aa
parenttarget-tricore: Added MADD.F and MSUB.F instructions (diff)
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target-tricore: Added new MOV instruction variant
Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. [BK: fix style error] [BK: Allocate temporaries only when needed] Signed-off-by: Peer Adelt <peer.adelt@c-lab.de> Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
-rw-r--r--target/tricore/translate.c16
-rw-r--r--target/tricore/tricore-opcodes.h1
2 files changed, 17 insertions, 0 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a8234dba83..1cdd87e8fb 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6034,6 +6034,8 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
uint32_t op2;
int r3, r2, r1;
+ TCGv temp;
+
r3 = MASK_OP_RR_D(ctx->opcode);
r2 = MASK_OP_RR_S2(ctx->opcode);
r1 = MASK_OP_RR_S1(ctx->opcode);
@@ -6224,6 +6226,20 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RR_MOV:
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
+ case OPC2_32_RR_MOV_64:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ temp = tcg_temp_new();
+
+ CHECK_REG_PAIR(r3);
+ tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
+ tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
+ tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
+
+ tcg_temp_free(temp);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_NE:
tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index df666b081f..78ba338640 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1062,6 +1062,7 @@ enum {
OPC2_32_RR_MIN_H = 0x78,
OPC2_32_RR_MIN_HU = 0x79,
OPC2_32_RR_MOV = 0x1f,
+ OPC2_32_RR_MOV_64 = 0x81,
OPC2_32_RR_NE = 0x11,
OPC2_32_RR_OR_EQ = 0x27,
OPC2_32_RR_OR_GE = 0x2b,