diff options
| author | Bin Meng | 2021-01-12 05:52:01 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-01-16 19:57:21 +0100 |
| commit | 56118ee88ddf0498e0c8c4c81ef91d793c76866f (patch) | |
| tree | ba062da720a30a0fcff7d7e4cd8a48c39628593a | |
| parent | hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite (diff) | |
| download | qemu-56118ee88ddf0498e0c8c4c81ef91d793c76866f.tar.gz qemu-56118ee88ddf0498e0c8c4c81ef91d793c76866f.tar.xz qemu-56118ee88ddf0498e0c8c4c81ef91d793c76866f.zip | |
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
In preparation to generate the CSR register list for GDB stub
dynamically, change csr_ops[] to non-static so that it can be
referenced externally.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.h | 8 | ||||
| -rw-r--r-- | target/riscv/csr.c | 10 |
2 files changed, 9 insertions, 9 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6339e84819..464653d70d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,14 @@ typedef struct { riscv_csr_op_fn op; } riscv_csr_operations; +/* CSR function table constants */ +enum { + CSR_TABLE_SIZE = 0x1000 +}; + +/* CSR function table */ +extern riscv_csr_operations csr_ops[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 10ab82ed1f..507e8ee763 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,14 +23,6 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" -/* CSR function table */ -static riscv_csr_operations csr_ops[]; - -/* CSR function table constants */ -enum { - CSR_TABLE_SIZE = 0x1000 -}; - /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) { @@ -1378,7 +1370,7 @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, } /* Control and Status Register function table */ -static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { +riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* User Floating-Point CSRs */ [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, [CSR_FRM] = { fs, read_frm, write_frm }, |