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| author | Andrew Jeffery | 2019-07-01 18:26:16 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-07-01 18:28:59 +0200 |
| commit | 58044b5cf5f30eb298709696ddbafdf547c1291c (patch) | |
| tree | 937fdc58114c448757c26e746c52b947654c4f93 | |
| parent | aspeed/timer: Fix behaviour running Linux (diff) | |
| download | qemu-58044b5cf5f30eb298709696ddbafdf547c1291c.tar.gz qemu-58044b5cf5f30eb298709696ddbafdf547c1291c.tar.xz qemu-58044b5cf5f30eb298709696ddbafdf547c1291c.zip | |
aspeed/timer: Status register contains reload for stopped timer
From the datasheet:
This register stores the current status of counter #N. When timer
enable bit TMC30[N * b] is disabled, the reload register will be
loaded into this counter. When timer bit TMC30[N * b] is set, the
counter will start to decrement. CPU can update this register value
when enable bit is set.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-9-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/timer/aspeed_timer.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 537f072cf8..8d6266b0fd 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -187,7 +187,11 @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg) switch (reg) { case TIMER_REG_STATUS: - value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + if (timer_enabled(t)) { + value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + } else { + value = t->reload; + } break; case TIMER_REG_RELOAD: value = t->reload; |