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author | Markus Armbruster | 2020-06-09 14:23:35 +0200 |
---|---|---|
committer | Markus Armbruster | 2020-06-15 21:36:21 +0200 |
commit | 589b1be07c060e583d9f758ff0cb10e0f1ff242f (patch) | |
tree | 85514177f64afb875f3e7bfe2c06a9b5c532bb13 | |
parent | riscv: Fix to put "riscv.hart_array" devices on sysbus (diff) | |
download | qemu-589b1be07c060e583d9f758ff0cb10e0f1ff242f.tar.gz qemu-589b1be07c060e583d9f758ff0cb10e0f1ff242f.tar.xz qemu-589b1be07c060e583d9f758ff0cb10e0f1ff242f.zip |
riscv: Fix type of SiFive[EU]SocState, member parent_obj
Device "riscv.sifive.e.soc" is a direct subtype of TYPE_DEVICE, but
its instance struct SiFiveESoCState's member @parent_obj is
SysBusDevice instead of DeviceState. Correct that.
Same for "riscv.sifive.u.soc"'s instance struct SiFiveUSoCState.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200609122339.937862-21-armbru@redhat.com>
-rw-r--r-- | include/hw/riscv/sifive_e.h | 2 | ||||
-rw-r--r-- | include/hw/riscv/sifive_u.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 414992119e..d386ea9223 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -29,7 +29,7 @@ typedef struct SiFiveESoCState { /*< private >*/ - SysBusDevice parent_obj; + DeviceState parent_obj; /*< public >*/ RISCVHartArrayState cpus; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 16c297ec5f..5f62cf5f85 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -31,7 +31,7 @@ typedef struct SiFiveUSoCState { /*< private >*/ - SysBusDevice parent_obj; + DeviceState parent_obj; /*< public >*/ CPUClusterState e_cluster; |