diff options
| author | LIU Zhiwei | 2022-01-20 13:20:48 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-21 06:52:57 +0100 |
| commit | 5a2ae2350e78cfdc7ca9885b8c3d62137115a494 (patch) | |
| tree | cca8810ec9efc3c956bf5c4d5d2297f29408405b | |
| parent | target/riscv: Adjust scalar reg in vector with XLEN (diff) | |
| download | qemu-5a2ae2350e78cfdc7ca9885b8c3d62137115a494.tar.gz qemu-5a2ae2350e78cfdc7ca9885b8c3d62137115a494.tar.xz qemu-5a2ae2350e78cfdc7ca9885b8c3d62137115a494.zip | |
target/riscv: Set default XLEN for hypervisor
When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a120d474df..1cb0436187 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -422,6 +422,16 @@ static void riscv_cpu_reset(DeviceState *dev) */ env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); + if (riscv_has_ext(env, RVH)) { + env->vsstatus = set_field(env->vsstatus, + MSTATUS64_SXL, env->misa_mxl); + env->vsstatus = set_field(env->vsstatus, + MSTATUS64_UXL, env->misa_mxl); + env->mstatus_hs = set_field(env->mstatus_hs, + MSTATUS64_SXL, env->misa_mxl); + env->mstatus_hs = set_field(env->mstatus_hs, + MSTATUS64_UXL, env->misa_mxl); + } } env->mcause = 0; env->pc = env->resetvec; |