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| author | Alistair Francis | 2020-12-16 19:22:56 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:44 +0100 |
| commit | 5c5a47f10ce8a65ab06b56d7912c7d4d58b287b6 (patch) | |
| tree | 9c23c35eee0ce900074f76f980d66d97dc650795 | |
| parent | target/riscv: Specify the XLEN for CPUs (diff) | |
| download | qemu-5c5a47f10ce8a65ab06b56d7912c7d4d58b287b6.tar.gz qemu-5c5a47f10ce8a65ab06b56d7912c7d4d58b287b6.tar.xz qemu-5c5a47f10ce8a65ab06b56d7912c7d4d58b287b6.zip | |
target/riscv: cpu: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
| -rw-r--r-- | target/riscv/cpu.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6f032122..47b738c314 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -240,10 +240,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); -#ifdef TARGET_RISCV32 - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", - (target_ulong)(env->mstatus >> 32)); -#endif + if (riscv_cpu_is_32bit(env)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", + (target_ulong)(env->mstatus >> 32)); + } if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", @@ -356,11 +356,12 @@ static void riscv_cpu_reset(DeviceState *dev) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { -#if defined(TARGET_RISCV32) - info->print_insn = print_insn_riscv32; -#elif defined(TARGET_RISCV64) - info->print_insn = print_insn_riscv64; -#endif + RISCVCPU *cpu = RISCV_CPU(s); + if (riscv_cpu_is_32bit(&cpu->env)) { + info->print_insn = print_insn_riscv32; + } else { + info->print_insn = print_insn_riscv64; + } } static void riscv_cpu_realize(DeviceState *dev, Error **errp) |