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| author | Philippe Mathieu-Daudé | 2021-10-19 10:20:04 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-11-02 14:32:32 +0100 |
| commit | 675bf34a6fe9db202edd49755c8c586764f5eabf (patch) | |
| tree | c1520f39be0541c66e8afd441443473ffc18cb2b | |
| parent | target/mips: Convert MSA 2RF instruction format to decodetree (diff) | |
| download | qemu-675bf34a6fe9db202edd49755c8c586764f5eabf.tar.gz qemu-675bf34a6fe9db202edd49755c8c586764f5eabf.tar.xz qemu-675bf34a6fe9db202edd49755c8c586764f5eabf.zip | |
target/mips: Convert MSA FILL opcode to decodetree
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-16-f4bug@amsat.org>
| -rw-r--r-- | target/mips/tcg/msa.decode | 2 | ||||
| -rw-r--r-- | target/mips/tcg/msa_translate.c | 31 |
2 files changed, 21 insertions, 12 deletions
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 33288b5035..bcbc573dee 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -27,6 +27,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @@ -82,6 +83,7 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + FILL 011110 11000000 .. ..... ..... 011110 @2r FCLASS 011110 110010000 . ..... ..... 011110 @2rf FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 704273dfd2..c750908898 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -61,7 +61,6 @@ enum { OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC, /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */ - OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R, OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R, OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R, OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R, @@ -1847,17 +1846,6 @@ static void gen_msa_2r(DisasContext *ctx) TCGv_i32 tws = tcg_const_i32(ws); switch (MASK_MSA_2R(ctx->opcode)) { - case OPC_FILL_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df == DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } -#endif - gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df), - twd, tws); /* trs */ - break; case OPC_NLOC_df: switch (df) { case DF_BYTE: @@ -1916,6 +1904,25 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(tws); } +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) +{ + if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { + /* Double format valid only for MIPS64 */ + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_fill_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); + + return true; +} + static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, gen_helper_piii *gen_msa_2rf) { |