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authorMatheus Ferst2022-06-29 18:29:02 +0200
committerDaniel Henrique Barboza2022-07-06 15:22:38 +0200
commit6addef4d272684ba624c9fcaf66bc67e5fc4a93f (patch)
treefd06588f778ae0be60c1a39828254bc237e7b5c5
parenttarget/ppc: Add flag for ISA v2.06 BCDA instructions (diff)
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target/ppc: implement addg6s
Implements the following Power ISA v2.06 instruction: addg6s: Add and Generate Sixes Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220629162904.105060-10-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
-rw-r--r--target/ppc/insn32.decode4
-rw-r--r--target/ppc/translate/fixedpoint-impl.c.inc37
2 files changed, 41 insertions, 0 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e5770bcc16..af8ba9ca9b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -311,6 +311,10 @@ CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
PDEPD 011111 ..... ..... ..... 0010011100 - @X
PEXTD 011111 ..... ..... ..... 0010111100 - @X
+## BCD Assist
+
+ADDG6S 011111 ..... ..... ..... - 001001010 - @X
+
### Float-Point Load Instructions
LFS 110000 ..... ..... ................ @D
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 1aab32be03..490e49cfc7 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -492,3 +492,40 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
+{
+ const uint64_t carry_bits = 0x1111111111111111ULL;
+ TCGv t0, t1, carry, zero = tcg_constant_tl(0);
+
+ REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
+
+ t0 = tcg_temp_new();
+ t1 = tcg_const_tl(0);
+ carry = tcg_const_tl(0);
+
+ for (int i = 0; i < 16; i++) {
+ tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4);
+ tcg_gen_andi_tl(t0, t0, 0xf);
+ tcg_gen_add_tl(t1, t1, t0);
+
+ tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4);
+ tcg_gen_andi_tl(t0, t0, 0xf);
+ tcg_gen_add_tl(t1, t1, t0);
+
+ tcg_gen_andi_tl(t1, t1, 0x10);
+ tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero);
+
+ tcg_gen_shli_tl(t0, t1, i * 4);
+ tcg_gen_or_tl(carry, carry, t0);
+ }
+
+ tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
+ tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(carry);
+
+ return true;
+}