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| author | Aurelien Jarno | 2009-05-04 09:54:57 +0200 |
|---|---|---|
| committer | Aurelien Jarno | 2009-05-04 10:05:21 +0200 |
| commit | 6bb72b184d7fe0e1e08f9cca722e78d1d24920c2 (patch) | |
| tree | 1e99e84c63f4d55d1804af399f18371b837500fc | |
| parent | target-mips: fix comments about SUB/DSUB (diff) | |
| download | qemu-6bb72b184d7fe0e1e08f9cca722e78d1d24920c2.tar.gz qemu-6bb72b184d7fe0e1e08f9cca722e78d1d24920c2.tar.xz qemu-6bb72b184d7fe0e1e08f9cca722e78d1d24920c2.zip | |
target-mips: proper sign extension for 'SUBU rd, zero, rt'
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-mips/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 2c163e0ca4..7ecc9fdaf3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1604,6 +1604,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); } else if (rs == 0 && rt != 0) { tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); } else if (rs != 0 && rt == 0) { tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); } else { |