diff options
| author | Bastian Koppelmann | 2014-09-01 13:59:56 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-09-01 15:49:21 +0200 |
| commit | 70b0226250db5ea5ec6c0bbc13514a3e27081c28 (patch) | |
| tree | f1ea3339837cb3b7d1f71431d8c5d81f8d91aa0a | |
| parent | target-tricore: Add instructions of SB opcode format (diff) | |
| download | qemu-70b0226250db5ea5ec6c0bbc13514a3e27081c28.tar.gz qemu-70b0226250db5ea5ec6c0bbc13514a3e27081c28.tar.xz qemu-70b0226250db5ea5ec6c0bbc13514a3e27081c28.zip | |
target-tricore: Add instructions of SBC and SBRN opcode format
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-12-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-tricore/translate.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index e13fba7087..1bd26421f8 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -391,6 +391,8 @@ static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { + TCGv temp; + switch (opc) { /* SB-format jumps */ case OPC1_16_SB_J: @@ -407,6 +409,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, case OPC1_16_SB_JNZ: gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); break; +/* SBC-format jumps */ + case OPC1_16_SBC_JEQ: + gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); + break; + case OPC1_16_SBC_JNE: + gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); + break; +/* SBRN-format jumps */ + case OPC1_16_SBRN_JZ_T: + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); + gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); + tcg_temp_free(temp); + break; + case OPC1_16_SBRN_JNZ_T: + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); + gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); + tcg_temp_free(temp); + break; default: printf("Branch Error at %x\n", ctx->pc); } @@ -716,6 +738,20 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); gen_compute_branch(ctx, op1, 0, 0, 0, address); break; +/* SBC-format */ + case OPC1_16_SBC_JEQ: + case OPC1_16_SBC_JNE: + address = MASK_OP_SBC_DISP4(ctx->opcode); + const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + break; +/* SBRN-format */ + case OPC1_16_SBRN_JNZ_T: + case OPC1_16_SBRN_JZ_T: + address = MASK_OP_SBRN_DISP4(ctx->opcode); + const16 = MASK_OP_SBRN_N(ctx->opcode); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + break; } } |