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| author | Alistair Francis | 2015-09-08 18:38:45 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-09-08 18:38:45 +0200 |
| commit | 7777b7a0ba27696ddf34a19818be17cc415551cc (patch) | |
| tree | 91a900a534dd0d296da8dc1c376ede30ebb42024 | |
| parent | target-arm: Add AArch64 access to PAR_EL1 (diff) | |
| download | qemu-7777b7a0ba27696ddf34a19818be17cc415551cc.tar.gz qemu-7777b7a0ba27696ddf34a19818be17cc415551cc.tar.xz qemu-7777b7a0ba27696ddf34a19818be17cc415551cc.zip | |
cadence_gem: Correct Marvell PHY SPCFC reset value
Bit 15 of the PHY Specific Status Register is reserved and
should remain 0. Fix the reset value to ensure that the 15th
bit is not set.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: c795069e49040ff770fe2ece19dfe1791b729e22.1441316450.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/net/cadence_gem.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 494a346cf6..1127223cfd 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s) s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; - s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00; + s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; s->phy_regs[PHY_REG_LED] = 0x4100; s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; |