diff options
| author | Knut Omang | 2014-08-24 15:32:18 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin | 2014-08-25 00:16:06 +0200 |
| commit | 821be9dbb220389eaa6857705e1df9e64888138f (patch) | |
| tree | ff4ddb7187b409abe1f0c12902faf1dfa087a612 | |
| parent | pcie: Fix incorrect write to the ari capability next function field (diff) | |
| download | qemu-821be9dbb220389eaa6857705e1df9e64888138f.tar.gz qemu-821be9dbb220389eaa6857705e1df9e64888138f.tar.xz qemu-821be9dbb220389eaa6857705e1df9e64888138f.zip | |
pcie: Rename the pcie_cap_ari_* functions to pcie_cap_arifwd_*
Rename helper functions to make a clearer distinction between
the PCIe capability/control register feature ARI forwarding and a
device that supports the ARI feature via an ARI extended PCIe capability.
Signed-off-by: Knut Omang <knut.omang@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/pci-bridge/ioh3420.c | 1 | ||||
| -rw-r--r-- | hw/pci-bridge/xio3130_downstream.c | 4 | ||||
| -rw-r--r-- | hw/pci/pcie.c | 11 | ||||
| -rw-r--r-- | include/hw/pci/pcie.h | 7 |
4 files changed, 13 insertions, 10 deletions
diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c index 7cd87fcbb4..aed2bf1d43 100644 --- a/hw/pci-bridge/ioh3420.c +++ b/hw/pci-bridge/ioh3420.c @@ -118,6 +118,7 @@ static int ioh3420_initfn(PCIDevice *d) if (rc < 0) { goto err_msi; } + pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s->slot); pcie_chassis_create(s->chassis); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 51f20d7467..b3a6479262 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -50,7 +50,7 @@ static void xio3130_downstream_reset(DeviceState *qdev) pcie_cap_deverr_reset(d); pcie_cap_slot_reset(d); - pcie_cap_ari_reset(d); + pcie_cap_arifwd_reset(d); pci_bridge_reset(qdev); } @@ -91,7 +91,7 @@ static int xio3130_downstream_initfn(PCIDevice *d) if (rc < 0) { goto err_pcie_cap; } - pcie_cap_ari_init(d); + pcie_cap_arifwd_init(d); rc = pcie_aer_init(d, XIO3130_AER_OFFSET); if (rc < 0) { goto err; diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index de0e967327..6cb6e0ca36 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -497,9 +497,10 @@ void pcie_cap_flr_write_config(PCIDevice *dev, } } -/* Alternative Routing-ID Interpretation (ARI) */ -/* ari forwarding support for down stream port */ -void pcie_cap_ari_init(PCIDevice *dev) +/* Alternative Routing-ID Interpretation (ARI) + * forwarding support for root and downstream ports + */ +void pcie_cap_arifwd_init(PCIDevice *dev) { uint32_t pos = dev->exp.exp_cap; pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, @@ -508,13 +509,13 @@ void pcie_cap_ari_init(PCIDevice *dev) PCI_EXP_DEVCTL2_ARI); } -void pcie_cap_ari_reset(PCIDevice *dev) +void pcie_cap_arifwd_reset(PCIDevice *dev) { uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); } -bool pcie_cap_is_ari_enabled(const PCIDevice *dev) +bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) { if (!pci_is_express(dev)) { return false; diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 7fe81f31ef..d139d588f6 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -103,9 +103,10 @@ void pcie_cap_flr_init(PCIDevice *dev); void pcie_cap_flr_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len); -void pcie_cap_ari_init(PCIDevice *dev); -void pcie_cap_ari_reset(PCIDevice *dev); -bool pcie_cap_is_ari_enabled(const PCIDevice *dev); +/* ARI forwarding capability and control */ +void pcie_cap_arifwd_init(PCIDevice *dev); +void pcie_cap_arifwd_reset(PCIDevice *dev); +bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev); /* PCI express extended capability helper functions */ uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id); |