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| author | Peter Maydell | 2019-04-29 18:35:58 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-04-29 18:35:58 +0200 |
| commit | 84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201 (patch) | |
| tree | 0ccca40492c0c20a79d9fe26124fd7223374a045 | |
| parent | target/arm: Make sure M-profile FPSCR RES0 bits are not settable (diff) | |
| download | qemu-84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201.tar.gz qemu-84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201.tar.xz qemu-84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201.zip | |
hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers
For M-profile the MVFR* ID registers are memory mapped, in the
range we implement via the NVIC. Allow them to be read.
(If the CPU has no FPU, these registers are defined to be RAZ.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-3-peter.maydell@linaro.org
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index ab822f4251..45d72f86bd 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1222,6 +1222,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return 0; } return cpu->env.v7m.sfar; + case 0xf40: /* MVFR0 */ + return cpu->isar.mvfr0; + case 0xf44: /* MVFR1 */ + return cpu->isar.mvfr1; + case 0xf48: /* MVFR2 */ + return cpu->isar.mvfr2; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); |