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| author | Philippe Mathieu-Daudé | 2020-12-16 23:59:07 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-01-14 17:13:53 +0100 |
| commit | 8b0ea9b638adadcf056f4a18fe53a7c6339beba8 (patch) | |
| tree | 25b77517bdd13f095f26af114b92b725f85c6b44 | |
| parent | target/mips/mips-defs: Reorder CPU_MIPS5 definition (diff) | |
| download | qemu-8b0ea9b638adadcf056f4a18fe53a7c6339beba8.tar.gz qemu-8b0ea9b638adadcf056f4a18fe53a7c6339beba8.tar.xz qemu-8b0ea9b638adadcf056f4a18fe53a7c6339beba8.zip | |
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
| -rw-r--r-- | target/mips/mips-defs.h | 8 | ||||
| -rw-r--r-- | target/mips/translate_init.c.inc | 14 |
2 files changed, 11 insertions, 11 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 48544ba73b..1630ae20d5 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -72,12 +72,12 @@ #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2) /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index cac3d24183..0ba3cf18ef 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -72,7 +72,7 @@ const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x1278FF17, .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32, + .insn_flags = CPU_MIPS32R1, .mmu_type = MMU_TYPE_R4000, }, { @@ -94,7 +94,7 @@ const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x1258FF17, .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .insn_flags = CPU_MIPS32R1 | ASE_MIPS16, .mmu_type = MMU_TYPE_FMT, }, { @@ -114,7 +114,7 @@ const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x1278FF17, .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32, + .insn_flags = CPU_MIPS32R1, .mmu_type = MMU_TYPE_R4000, }, { @@ -134,7 +134,7 @@ const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x1258FF17, .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .insn_flags = CPU_MIPS32R1 | ASE_MIPS16, .mmu_type = MMU_TYPE_FMT, }, { @@ -552,7 +552,7 @@ const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 36, - .insn_flags = CPU_MIPS64, + .insn_flags = CPU_MIPS64R1, .mmu_type = MMU_TYPE_R4000, }, { @@ -578,7 +578,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 42, .PABITS = 36, - .insn_flags = CPU_MIPS64, + .insn_flags = CPU_MIPS64R1, .mmu_type = MMU_TYPE_R4000, }, { @@ -607,7 +607,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 40, .PABITS = 36, - .insn_flags = CPU_MIPS64 | ASE_MIPS3D, + .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D, .mmu_type = MMU_TYPE_R4000, }, { |