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| author | Philippe Mathieu-Daudé | 2020-11-26 11:54:56 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-01-14 17:13:53 +0100 |
| commit | 9a7372e35491fc4c8f0bb20359dda87626bdf831 (patch) | |
| tree | 15719c2532cc54b81ea2a113595ee60363410342 | |
| parent | target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree (diff) | |
| download | qemu-9a7372e35491fc4c8f0bb20359dda87626bdf831.tar.gz qemu-9a7372e35491fc4c8f0bb20359dda87626bdf831.tar.xz qemu-9a7372e35491fc4c8f0bb20359dda87626bdf831.zip | |
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-10-f4bug@amsat.org>
| -rw-r--r-- | target/mips/mips32r6.decode | 5 | ||||
| -rw-r--r-- | target/mips/translate.c | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode index 543e0c77bb..cb86877490 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/mips32r6.decode @@ -20,5 +20,10 @@ REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 +REMOVED 100010 ----- ----- ---------------- # LWL +REMOVED 100110 ----- ----- ---------------- # LWR +REMOVED 101010 ----- ----- ---------------- # SWL +REMOVED 101110 ----- ----- ---------------- # SWR + REMOVED 101111 ----- ----- ---------------- # CACHE REMOVED 110011 ----- ----- ---------------- # PREF diff --git a/target/mips/translate.c b/target/mips/translate.c index 381571e45b..d9d9952f88 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28588,11 +28588,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_LWL: case OPC_LWR: - check_insn_opc_removed(ctx, ISA_MIPS_R6); - /* Fallthrough */ case OPC_LB: case OPC_LH: case OPC_LW: @@ -28603,8 +28602,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_SWL: case OPC_SWR: - check_insn_opc_removed(ctx, ISA_MIPS_R6); - /* fall through */ case OPC_SB: case OPC_SH: case OPC_SW: |